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1 International Journal of Microelectronics and Computer Science

1 2010

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Digitally programmable delay-locked-loop with variable charge pump current

Lopes B., Paulino N., Goes J., Steiger-Garçăo A.

International Journal of Microelectronics and Computer Science

2010

Vol. 1, nr 3

269-276

This paper presents a digitally programmable delay line intended for use as timing generator in a RADAR ranging system. The architecture of the programmable delay uses a ΣΔ modulator to generate a reference clock with a delay unaffected by component matching. This reference clock has a large jitter noise component that is filtered by delay lock loop (DLL). The programmable delay can produce a delay ranging from 20 ns to 100 ns, because of the large delay variation, it is necessary to use a variable charge pump current in the DDL, in order to guaranty stability for all the desired delay values. The electrical design of the circuit, in a 0.13-/žm 1.2-V CMOS technology, will be presented, as well as electrical simulations results of the complete system.