Encapsulated tunable electromechanical oscillators are a milestone on the road to smart dust sensor nodes. To foster the advent of ultrahigh system sensitivity thanks to novel technologies, a computationally light analytical and semi-empirical model for carbon nanotube resonator dynamics, electromechanical and piezoresistive properties is presented. This model is the breeding ground for the subsequent design and integration of a phase locked loop and feedback circuitry, which form an adaptive closed-loop oscillator for actuation, detection and sustainment of the nanotube’s motion. Closed-loop operation and tube stretching make the system Widely universal and invariant to spreads in nanotube characteristics.
Hybrid NEMS interfaces are the key to systems combining the benefits of highly sensitive miniaturized mechanical sensors with the vast functionalities available in electronics. In this context, a phase-locked loop, locking on a suspended resonating carbon nanotube NEMS, is implemented and characterized, able to start, track, amplify and sustain NEMS oscillation up to 100MHz in a sensing environment. Detection of the signals out of the NEMS has been found most challenging and diverse RF front-ends meant for interfacing high-impedance carbon nanotube based NEMS are analyzed. Given the feeble signals from the NEMS, their high output impedance and non-negligible interconnect parasitics, front-end design must imperatively focus on minimal noise figure. Limits on minimal detectable signal are extracted via design, simulation and characterization of a 3-stage common-emitter front-end.
This paper presents a methodology for digitally calibrating analog circuits and systems. Based on the detection of an imperfection by a simple comparator, a successive approximations algorithm tunes a compensation current. The latter is generated by a sub-binary radix M/2+M DAC, which has the advantage of allowing reaching arbitrarily high resolutions at the cost of extremely small area. The methodology proposed allows the removal of any type of imperfections, at the expense of two shift registers, a few logical gates and a DAC which is smaller than the shift register.
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