Wyniki wyszukiwania - BazTech

Ograniczanie wyników

Znaleziono wyników: 2

Liczba wyników na stronie

Wyniki wyszukiwania

Sortuj według:

Ogranicz wyniki do:

100 Gb/s Data Link Layer - from a Simulation to FPGA Implementation

Łopaciński Ł., Brzozowski M., Kraemer R., Buechner S., Nolte J.

Journal of Telecommunications and Information Technology

2016

nr 1

90--100

In this paper, a simulation and hardware implementation of a data link layer for 100 Gb/s terahertz wireless communications is presented. In this solution the overhead of protocols and coding should be reduced to a minimum. This is especially important for high-speed networks, where a small degradation of efficiency will lower the user data throughput by several gigabytes per second. The following aspects are explained: an acknowledge frame compression, the optimal frame segmentation and aggregation, Reed-Solomon forward error correction, an algorithm to control the transmitted data redundancy (link adaptation), and FPGA implementation of a demonstrator. The most important conclusion is that changing the segment size influences the uncoded transmissions mostly, and the FPGA memory footprint can be significantly reduced when the hybrid automatic repeat request type II is replaced by the type I with a link adaptation. Additionally, an algorithm for controlling the Reed-Solomon redundancy is presented. Hardware implementation is demonstrated, and the device achieves net data rate of 97 Gb/s.

100 Gbps wireless – data link layer VHDL implementation

Lopacinski L., Nolte J., Buechner S., Brzozowski M., Kraemer R.

Measurement Automation Monitoring

2015

Vol. 61, No. 7

333--336

In this paper, we describe implementation and hardware used for a wireless 100 Gbps data link layer demonstrator. So fast stream processing requires a highly parallelized approach. The timing requirements of the 100 Gbps networks are so demanding that there is no chance to deal with this task as a single stream in a field programmable gate array (FPGA). Due to this reason, we introduce and validate one of possible architectures that can solve the task. The 100 Gbps implementation is explained in detail, and the most important parameters of the FPGA design are mentioned.