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Simple modeling approach for line impedance of on-chip CMOS interconnects

Ymeri H., Nauwelaers B., Maex K.

Journal of Technical Physics

2004

Vol. 45, no 1

71-77

Simple and accurate closed-form model enabling to calculate frequency-dependent distributed inductance and associated distributed series resistance per-unit-length of single on-chip interconnects on a lossy silicon substrate is presented. The closed-form formulas for the frequency-dependent series impedance parameters are obtained using a closed-form integration method and the vector magnetic potential equation. The proposed frequency-dependent inductance -L(omega) and resistance R(omega) per-unit-length formulas are shown to be in good agreement with the electromagnetic solutions.

Efficient procedure for capacitance matrix calculation of multilayer VLSI interconnects using quasi-static analysis and Fourier series approach

Ymeri H., Nauwelaers B., Maex K.

Journal of Telecommunications and Information Technology

2002

nr 2

40-44

In this paper, we present a new approach for capacitance matrix calculation of lossy multilayer VLSI interconnects based on quasi-static analysis and Fourier projection technique. The formulation is independent from the position of the interconnect conductors and number of layers in the structure, and is especially adequate to model 2D and 3D layered structures with planar boundaries. Thanks to the quasi-static algorithms considered for the capacitance analysis and the expansions in terms of convergent Fourier series the tool is reliable and very efficient; results can be obtained with relatively little programming effort. The validity of the technique is verified by comparing its results with on-surface MEI method, moment method for total charges in the structure, and CAD-oriented equivalent-circuit methodology, respectively.