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Spice simulation of substrate potential shift in HVCMOS technologies

Stefanucci C., Buccella P., Kayal M., Sallese J.-M.

International Journal of Microelectronics and Computer Science

2015

Vol. 6, nr 4

142--147

High voltage CMOS active devices inherently include a parasitic vertical PNP bipolar transistor. When activated it injects holes into the substrate causing a dangerous potential shift. In this work a spice-modeling approach based on transistor layout is presented to simulate substrate de-biasing in Smart Power ICs. The proposed model relies on a parasitic substrate network without the need of a parasitic BJT in HVCMOS compact models. The results are compared with TCAD simulations at different temperatures showing good agreement. Potential shift of the substrate is analysed for different geometrical configurations to estimate the effect of P+ grounding schemes and backside contact.

SPICE simulation of passive N-type guard rings in smart power ICs

Buccella P., Stefanucci C., Sallese J.-M., Kayal M.

International Journal of Microelectronics and Computer Science

2015

Vol. 6, nr 2

64--68

When designing in Smart Power technologies, TCAD simulations are mandatory to design effective passive protections against parasitic couplings due to minority carriers. The objective of this paper is to propose a SPICE-based approach to characterize electrical key parameters of a passive protection directly within standard IC design flow avoiding time consuming TCAD simulations. Our approach consists in integrating a new substrate model in SPICE to enable designers to derive themselves process specific design rules and reduce substrate couplings. This methodology enables designers to access valuable results in the early stage of IC design, where before such results could be obtained only in the final verification step.

Inﬂuence of substrate meshing on the accuracy of EPFL substrate model for smart power ICs

Stefanucci C, Buccella P, Kayal M., Sallese J.M.

International Journal of Microelectronics and Computer Science

2014

Vol. 5, nr 2

61--68

Minority carriers diffusion in Smart Power ICs substrate can be simulated in standard spice-like software using the EPFL Substrate Model. This model is based on a parasitic substrate network extracted from the integrated circuit layout following a given meshing strategy. In this work Design of Experiments (DOE) techniques are used to run a limited number of simulations to evaluate the inﬂuence of the meshing strategy on the accuracy of the model when compared to Technology Computer Aided Design (TCAD) simulations. A parasitic lateral BJT will be analyzed as two-dimensional case study with both spice-like and ﬁnite element simulations for the minority carriers diffusion. Using statistical analysis a linear model is developed to discover the main geometrical domains inﬂuencing the accuracy of the studied model.

Extraction of an equivalent electrical circuit for SPICE simulation of substrate minority carriers propagation

Buccella P, Stefanucci C, Sallese J.M., Kayal M.

International Journal of Microelectronics and Computer Science

2014

Vol. 5, nr 2

47--53

This paper presents an equivalent electrical circuit for substrate minority carriers SPICE simulation. The electrical circuit parameters are extracted from substrate meshing applying the ﬁnite difference method. This model is derived from a linearization of drift-diffusion equations and not from the closed form solution. Further, the proposed circuit is solved with available SPICE simulators because of electrical analogies with physical quantities. As a result, the minority carrier diffusion current is included automatically in the total substrate current computation. SPICE simulation results are compared with device simulator results for the one and three-dimensional cases.