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1 2023

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Realization of multiplexer logic-based 2-D block firfilter using distributed arithmetic

Chowdari Ch. Pratyusha, Seventline J. Beatrice

Computer Assisted Methods in Engineering and Science

2023

Vol. 30, no. 1

89--103

This paper presents a novel systolic two-dimensional (2D) block finite impulse response(FIR) filter architecture using a distributed arithmetic (DA)-based multiplexer look-uptable (DA-MUX-LUT). The proposed DA-MUX-LUT architecture computes the instan-taneous partial-product using the bit vector. The switching-based LUT replaces memory-based structures and reduces hardware complexity. Block processing allows memory reuse,which reduces the number of registers to store the previous input samples. Parallel addersare substituted by a modified carry look-ahead adder (MCLA), which minimizes the delay.Moreover, a resource-sharing concept is introduced to the DA-MUX-LUT block that drastically reduces the adder requirement. The application specific integrated circuit (ASIC)synthesis results show that the proposed DA-MUX-LUT-based 2-D block FIR filter forfilter size 8x8 and block size 4 has 31.22% less delay, 28.66% less area-delay product(ADP), 37.70% less power-delay product (PDP), and occupies almost the same area thanthe existing architecture.