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FPGA Based Digital Electronic Education, Clock-Calendar Design

Kiray V., Zhaparov M.

Przegląd Elektrotechniczny

2013

R. 89, nr 4

185-189

The clock calendar design is a case study produced in a project called FPGA based Digital Electronic Education Project (FPGA_b_deep.) The aim of the project is to develop case studies named “instructive and attractive examples” for Project Based Learning (PBL) to obtain high performance at Digital Design Education for electronics/computer engineering students or new digital circuit designers. The clock-calendar Design is second one from the instructive and attractive examples series and it is aimed students to enhance their skills of using counter, multiplexer, comparator and decoder while completing this design. The design of the clock calendar is completed considering the level of students and tested, then divided into three main blocks considering the criteria towards education. Graphic design is preferred for better understanding instead the design with HDL.

W artykule opisano proponowane zajęcia projektowe dla studentów elektroniki i inżynierii komputerowej. Zadanie polega na zaprojektowaniu zegarka i kalendarza z wykorzystaniem układu FPGA. Projekt ma na celu zaznajomienie uczestników zajęć z zagadnieniami projektowania układów logicznych. W projekcie wykorzystywany jest tryb schematyczny.

FPGA Based Digital Electronic Education, Data Entry Organization for a Calculator

Kiray V.

Przegląd Elektrotechniczny

2012

R. 88, nr 11a

200-204

In this study, an example is presented developed under a Project named FPGA based Digital Electronics Education Project (FPGA_b_DEEP). The Project aims to develop instructive and attractive examples to teach Digital Electronics effectively and faster. In the ex ample developed in this study, a data entry organization part of an 8 bits calculator design is dealt with. The design is prepared by considering students/New designers' knowledge level and divided into four parts for better understanding. The functions implemented in the modules are to code a number Or an arithmetic operation to each button, to shift the numbers to left side with each entered digit of number, to multiply the digits with proper coefficients from decimal numbering system, to parallel add the multiplied digits with the proper coefficients, to create the number from entered digits AT electronics environment (in a 32 bits register).

W artykule przedstawiono program szkoleniowy dla studentów, dotyczący projektowania kalkulatora w układzie FPGA (ang. Field Programmable Gate Array).