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EN
Hardware implementations of cryptographic algorithms are ubiquitous in contemporary computer systems where they are used to ensure appropriate level of security e.g. in high-speed data transmission, authentication and access control, distributed cloud storage, etc.. In this paper we evaluate size and speed efficiency of FPGA implementations of selected popular cryptographic algorithms in the newest cost-sensitive Spartan-7 devices form Xilinx, Inc.. The investigated set of algorithms included four examples: the AES-128 standard symmetric block cipher, the BLAKE-256 hash function and two size variants of the KECCAK-f[b] compression function, b = 400 and 1600, with the larger variant being used as the core of the new SHA-3 standard. The main aim of this research was to provide a uniform and comparable implementation approach for all the ciphers so that the new potentials of the Spartan-7 internal architecture would be put to the test in realization of their specific cryptographic transformations and data distribution. Each of the four algorithms was implemented in five architectures: the basic iterative one (with one instance of the cipher round instantiated in hardware) plus two loop unrolled ones (with two and four or five rounds in hardware) and their two pipelined variants (with registers at the outputs of each round enabling parallel processing of multiple streams of data). Uniform implementation methodology applied to 20 cases of cipher & architecture combinations created a consistent testbed, producing comparable results which allowed to evaluate efficiency of the new hardware platform in implementation of the different algorithms in various unrolled and pipelined organizations.
EN
In contemporary computer systems security issues are very important for both safety and reliability reasons thus application of appropriate cryptographic methods is a necessity in system design and maintenance. This paper deals with one such method – BLAKE hash function – and investigates its implementation in hardware. The algorithm was a candidate proposed for the SHA-3 contest and, although it was not selected in the final round as the winner, it was very well received for its cryptographic strength and performance, being still used as a hash method of choice in contemporary IT systems. In this paper we discuss a specific modification in hardware realizations of the function which eliminates need for involved data paths distributing message bits among the round units by using auxiliary memory modules for repetitive storage of the message inside each round instance. The idea was implemented in realizations of both BLAKE and BLAKE2 versions of the algorithm in four different organizations: the standard iterative one and three high-speed loop-unrolled architectures with 2, 4 and 5 rounds instantiated in hardware. Together with standard (without RAM) implementations this produced a total of 16 test cases: after implementation in a popular Spartan-3 device from Xilinx their parameters allowed for exhaustive evaluation of the proposed modification. The results reveal that the modification outstandingly enhances size of all the tested architectures: on average, occupation of the FPGA array is reduced at least by half while the improvements in speed, although not so spectacular, are also visible. Additional analyses indicate that the method can also increase overall efficiency of routing, helps in implementation of the loop-unrolled architectures and strengthens optimizations introduced by the BLAKE2 version of the algorithm.
EN
BLAKE is a cryptographic hash function proposed as a candidate in SHA-3 contest where he successfully qualified to the final round with other 4 candidates. Although it eventually lost to KECCAK it is still considered as a suitable solution with good cryptographic strength and great performance especially in software realizations. For these advantages BLAKE is commonly selected to be a hash function of choice in many contemporary IT systems in applications like digital signatures or message authentication. The purpose of this paper is to evaluate how the algorithm is suitable to be implemented in hardware using low-cost Field Programmable Gate Array (FPGA) devices, particularly to test how efficiently its complex internal transformations can be realized with FPGA resources when overall size of the implementation grows substantially with multiple rounds of the cipher running in parallel in hardware and capacity of the configurable array is used up to its limits. The study was made using the set of 7 different architectures with different loop unrolling factors and with optional application of pipelining, with each architecture being implemented in two popular families of FPGA devices from Xilinx. Investigation of the internal characteristic of the implementations generated by the tools helped in analysis how the fundamental mechanism of loop unrolling with or without pipelining works in case of this particular cipher.
EN
The aim of this paper is to test efficiency of automatic implementation of selected cryptographic algorithms in two families of popular-grade FPGA devices from Xilinx: Spartan-3 and Spartan-6. The set of algorithms include the Advanced Encryption Standard (AES) used worldwide as a symmetric cipher along with two hash algorithms: Salsa20 (developed with ECRYPT Stream Cipher Project) and Keccak permutation function (core of the new SHA-3 standard). The ciphers were expressed in 5 architectures: the basic iterative one (one instance of a round in hardware) and its four derivatives created by loop unrolling and pipelining. With each of the architectures implemented in both Spartan devices this gave the total of 30 test cases, which, upon automatic implementation, created a comprehensive and consistent base for comparison of the ciphers, applied architectures and FPGA devices used for implementation.
EN
Salsa20 is a 256-bit stream cipher that has been proposed to eSTREAM, ECRYPT Stream Cipher Project, and is considered to be one of the most secure and relatively fastest proposals. This paper describes hardware implementation of various architectures of this cipher in popular Field Programmable Gate Arrays (FPGA). The implemented architectures are based on the loop-unrolled data flow organization and after pipelining they can reach the throughput in the range of 20 – 30 Gbps even after fully automatic implementation in popular low-cost families of Spartan-3 and Spartan-6 from Xilinx. More resource-limited iterative architectures achieve speed of 1 – 2 Gbps. The results that are included in this work present potential of the algorithm when it is implemented in a specific FPGA environment and provide some information for evaluation of cipher effectiveness in contemporary popular programmable devices.
EN
In this paper, we present an approach which allows evaluation of various possible maintenance scenarios with respect to both reliability and economic criteria. The method is based on the concept of a life curve and discounted cost used to study the effect of equipment aging under different maintenance strategies. The deterioration process is first described by a Markov model and then its various characteristics are used to develop the equipment life curve and to quantify other reliability parameters. Based on these data, effects of various “what-if” maintenance scenarios can be examined and their efficiency compared. Simple life curves are combined to model equipment deterioration undergoing diverse maintenance actions, while computing other parameters of the model allows evaluation of additional critical factors, such as the probability of equipment failure. Additionally, the paper deals with the problem of the model adjustment so that the computed repair frequencies are close to the historical values, which is very important in practical applications of the method. Moreover, we discuss the problems which may arise if automatic adjustment is used in cases when the hypothetical maintenance policies go beyond the conditions upon which the original model was built.
PL
Przedmiotem artykułu jest modelowanie różnych możliwych scenariuszy eksploatacyjnych maszyn i urządzeń, które uwzględnia kryteria zarówno niezawodnościowe, jak i ekonomiczne. Metoda opiera się na zastosowaniu krzywych życia (ang. life curves) oraz kosztów zdyskontowanych (ang. discounted costs) do analizy wpływu, jaki różne strategie eksploatacyjne wywierają na starzenie się sprzętu. Punktem wyjścia jest opisanie procesu starzenia przez model Markowa, którego charakterystyki umożliwiają następnie wyznaczenie kształtu krzywej życia oraz obliczenie innych parametrów niezawodnościowych badanego sprzętu. W oparciu o uzyskane dane możliwa jest ocena różnych hipotetycznych scenariuszy eksploatacyjnych oraz porównanie ich efektywności. Proste krzywe życia mogą być łączone ze sobą w celu wizualizacji starzenia sprzętu poddawanego różnorodnym możliwym czynnościom naprawczym, natomiast obliczenie innych charakterystyk modelu pozwala wyznaczyć dodatkowe ważne parametry, takie jak prawdopodobieństwo uszkodzenia. Dodatkowo artykuł opisuje zagadnienie korygowania parametrów modelu, tak aby obliczane w nim częstości napraw sprzętu były bliskie wartościom znanym z jego historii eksploatacji, co jest bardzo ważne w praktycznych zastosowaniach metody. Omawiamy także problemy mogące pojawić się, gdy algorytm automatycznego korygowania modelu jest stosowany w analizach hipotetycznych strategii eksploatacyjnych wykraczających poza warunki, dla których model oryginalny został opracowany.
EN
In this paper we discuss hardware implementations of the two best ciphers in the AES contest – the winner Rijndael and the Serpent – in low-cost, popular Field-Programmable Gate Arrays (FPGA). After presenting the elementary operations of the ciphers and organization of their processing flows we concentrate on specific issues of their implementations in two selected families of popular-grade FPGA devices from Xilinx: currently the most common Spartan-6 and its direct predecessor Spartan-3. The discussion concentrates on differences in resources offered by these two families and on efficient implementation of the elementary transformations of the two ciphers. For case studies we propose a selection of different architectures (combinational, pipelined and iterative) for the encoding units and, after their implementation, we compare size requirements and performance parameters of the two ciphers across different architectures and on different FPGA platforms.
EN
Reliable operation of contemporary complex systems depends on selecting efficient maintenance policy, which often must take into account not only the reliability, but also economic factors. In this work, we present an approach which allows evaluation of various possible maintenance scenarios with respect to these two areas. The method is based on the concept of a life curve and discounted cost used to study the effect of equipment aging under different maintenance strategies. The deterioration process is first described by a Markov model and then its various characteristics are used to develop the equipment life curve and to quantify other reliability parameters. Based on these data, effects of various “what-if” maintenance scenarios can be examined and their efficiency compared. Simple life curves are combined to model equipment deterioration undergoing diverse maintenance actions, while computing other parameters of the model allows evaluation of additional critical factors, such as probability of equipment failure. Additionally, the paper deals with the problem of the model adjustment so that the computed frequencies are close to the historical values, which is very important in practical applications of the method.
9
Content available remote Triangulation of NURBS surfaces through adaptive refinement
EN
This paper discusses adaptive approach to the problem of automatic triangulation of NURBS surfaces. The algorithm presented here generates triangulation through the so-called adaptive refinement - a process carried out entirely in a parametric space with a variable triangle size adjucted to the local curvature of the surface, so that the imposed approximation error is not exceeded. The mesh is generated as an adaptive one right from the start, and no further decimation is required. Sample triangulations generated by the algorithm as well as a discussion of its computational complexity are included. Running times of the computer implementation confirm that an average computational cost of the algorithm is ~ O (N), with N denoting the total number of traingles in the final mesh.
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