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EN
The paper presents column parallel signal processing techniques for reducing Random Telegraph Signal (RTS) noise of in-pixel source follower by using histogram analysis for the development of a very low-noise CMOS image sensor. In this method, a histogram with multiple samples for reset level is used to estimate the amplitude of the RTS noise. With the median of the histogram and the estimated amplitude, the RTS noise components are removed and the average is calculated with the histogram due to thermal noise only, to further reduce the noise level. Result of the application of the histogram-based noise suppres-sion to an implemented CMOS image sensor prototype for a large sampling numbers is demonstrated.
EN
In this paper a new method of linearized settling error calibration for a pipeline A/D converter is proposed. The pipeline A/D converter employs non-slewing amplifiers for linearizing the settling error. A prototype 15b pipeline A/D converter was fabricated in 0.25 µm process. The calibration is carried out by adjusting gradients and offsets of the linearized settling error. The calibration of the settling error improves the SNDR and SFDR from 68 dB and 74 dB to 72 dB and 88 dB, respectively, at 35MS/s.
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