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2 Zubrzycka-Singh Weronika

2 2025

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Low-noise high-resolution CMOS readout ASIC for silicon strip X-ray detectors

Zubrzycka-Singh Weronika

Opto-Electronics Review

2025

Vol. 33, No. 4

art. no. e156670

This work presents the design, characterisation, and measurement results of the silicon strip sensor readout circuit for X-ray applications. The key design goals were a noise level below 50 electrons rms, low power consumption (below 10 mW per channel) and a compact layout. The prototype integrated circuit was designed and fabricated in a 180 nm CMOS technology, incorporating eight charge-processing channels, biasing circuits, reset and baseline restoration logic, and a calibration system.

LNSTRIP read-out ASIC for the X-ray strip detectors

Zubrzycka-Singh Weronika

International Journal of Electronics and Telecommunications

2025

Vol. 71, No. 4

The X-ray imaging systems dedicated for X-ray spectroscopy, based on a semiconductor strip sensors have been recently an important research topic. The most important research objective is working towards improvement of the spectroscopic and position resolution features [1]-[3]. In spectroscopic applications the short strip silicon detectors are widely used due to their relatively small capacitance and leakage current. Using strip pitch below 75 μm enables achievement of high spatial resolution. In this work, the analysis and design of the read-out electronics for the short silicon strip detectors are presented. The Charge Sensitive Amplifier (CSA) is optimized for the detector capacitance of about 1.5 pF, and the shaping amplifier default peaking time is about 1 μs (controlled by the sets of switches). To achieve the lowest possible noise level, the sources of noise in a radiation imaging system both internal (related to the front-end electronics itself), as well as external, were considered [4]. We target the noise level below 40 el. rms, considering low power consumption (a few mW) and limited channel area. To increase the speed of incoming hits processing, the continuous-time resistive CSA feedback together with a digital feedback reset are included. The prototype integrated circuit comprises of 8 charge processing channels, biasing circuits, reset and base-line restoration logic, and a calibration circuit.