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1 1998

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A design technique for polyphase decimators with binary constrained coefficients for high resolution A/D converters

Krukowski A., Kale I., Morling R., Hejn K.

Prace Przemysłowego Instytutu Elektroniki

1998

nr 132

53-56

This paper presents a design technique for liigh fidelity multistage decimation filters based on the polyphase and decimator structures presented in [1][2], catering for powers of two sample-rate decreases. The technique is well suited for Analog-to-Digital Converter (ADC) applications in excess of 16 bit resolution. The resulting filter coefficients are constrained to the required bit length using a "bit tipping algorithm" [3]. This technique is comparatively presented through an example of a cascaded decimation filter, designed for a 20-bit resolution ADC and compared to with other approximation methods. The coefficients and frequency responses of the cascaded filler are reported.