Wyniki wyszukiwania - BazTech

1

Evaluation of Selected Timing Parameters of FPGA Device

Sondej D., Szymanowski R., Szplet R.

Measurement Automation Monitoring

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2018

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Vol. 64, No. 1

23--25

EN

We present a method and results of measurements of FPGA (Field Programmable Gate Array) selected timing parameters crucial in many timing sensitive applications such as precise time and frequency metrology. Two main parameters, i.e. the delay and its jitter, were evaluated for look-up-tables (delay 740 ps/jitter 1.33 ps), IO buffers (na/0.45 ps) and carry-chain multiplexers (28ps/0.153 ps) integrated in a programmable device Spartan-6 (Xilinx) which is one of most popular FPGA chips on the market now. Measurements were performed with the use of fast real-time sampling oscilloscope.

2

Digital-to-Time Converter for pulse train generation based on Look-Up Tables in FPGA

Kwiatkowski P., Różyc K., Szplet R.

Measurement Automation Monitoring

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2018

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Vol. 64, No. 1

14--16

EN

A Digital-to-Time Converter (DTC) is presented which allows to generate pulse train with resolution of 250 ps within 32 ns operation range. The converter is implemented in off-the-shelf Spartan-6 Field-Programmable Gate Array (FPGA) device, manufactured by Xilinx in 45 nm CMOS technology. The design is implemented with the use of Look-Up Tables (LUT) as delay elements. “Manual” Place and Route (P&R) process was involved to improve conversion linearity. Developed DTC can be used to improve the functionality of time interval generators.

3

Stanowisko do badań termicznych z dedykowanym oprogramowaniem

Grzęda G., Kwiatkowski P., Szplet R.

Elektronika : konstrukcje, technologie, zastosowania

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2018

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Vol. 59, nr 1

5--9

PL

W artykule opisano stanowisko do automatycznych badań termicznych liczników czasu. Wyniki uzyskane w zakresie od -10°C do +45°C pozwalają określić wpływ zmian temperatury na parametry metrologiczne takie jak rozdzielczość, precyzja oraz błąd niezrównoważenia torów pomiarowych. Wykonane stanowisko z dedykowanym, uniwersalnym oprogramowaniem umożliwia automatyzacje procesu badań termicznych nowoopracowywanych urządzeń do pomiaru odcinków czasu.

EN

The article describes test setup for automatic thermal experiments of time interval counters. The obtained results within the range from -10°C to +45°C allow to define thermal influence on metrological parameters such as resolution, precision and offset. The test setup with dedicated, universal software enables automatic execution of thermal tests for newly designed equipment for time metrology.

4

Zautomatyzowane stanowisko do identyfikacji charakterystyki przetwarzania precyzyjnego generatora odcinków czasu

Grzęda G., Kwiatkowski P., Szplet R., Różyc K., Jachna Z.

Przegląd Elektrotechniczny

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2017

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R. 93, nr 12

277--280

PL

Przedstawiono budowę, zasadę działania oraz wyniki badań zautomatyzowanego stanowiska do identyfikacji charakterystyki przetwarzania precyzyjnego generatora odcinków czasu. Z uwagi na bardzo dużą liczbę nastaw syntezera DDS użytego do budowy generatora, wyznaczenie tej charakterystyki w drodze pomiarów wykonywanych manualnie jest bardzo czasochłonne. Duża powtarzalność uzyskanych wyników umożliwia zapis wyznaczonej charakterystyki przetwarzania w pamięci generatora i wybór odpowiednich nastaw pozwalających uzyskać najmniejsze rozmycie czasowe wytwarzanych odcinków czasu.

EN

We present the design, principle of operation and test results obtained in automated test setup for transfer characteristic recognition of precise time interval generator. Due to a very large number of phase steps in DDS synthesizer that was used in the generator, manual measurement process is time consuming and automatic test setup is recommended. As the obtained results are highly repeatable it can be used to build an array of DDS phase settings that ensure lowest timing jitter of output pulses.

5

5 ps Jitter Programmable Time Interval/Frequency Generator

Kwiatkowski P., Różyc K., Sawicki M., Jachna Z., Szplet R.

Metrology and Measurement Systems

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2017

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Vol. 24, nr 1

57--68

EN

A new time interval/frequency generator with a jitter below 5 ps is described. The time interval generation mechanism is based on a phase shifting method with the use of a precise DDS synthesizer. The output pulses are produced in a Spartan-6 FPGA device, manufactured by Xilinx in 45 nm CMOS technology. Thorough tests of the phase shifting in a selected synthesizer are performed. The time interval resolution as low as 0.3 ps is achieved. However, the final resolution is limited to 500 ps to maximize precision. The designed device can be used as a source of high precision reference time intervals or a highly stable square wave signal of frequency up to 50 MHz.

6

Estimation of quantization steps of time interpolator in view of temperature changes

Sondej D., Szplet R.

Measurement Automation Monitoring

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2017

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Vol. 63, No. 5

192--194

EN

This paper presents a method of limiting the effect of ambient temperature drift on the measurement uncertainty of a time counter (TC). A change in ambient temperature causes a change in the TC transfer function, i.e. the widths of quantization steps to be exact. Recalibration is a procedure that is then required, but it disturbs the measurement process. However, with the knowledge of the current ambient temperature and having the set of transfer functions identified at different temperatures, it is possible to determine and use the most adequate transfer function and virtually eliminate the temperature impact. For this purpose, three interpolation methods were studied: the nearest neighbor method, linear and polynomial interpolations. A newly evaluated transfer functions were tested in interpolating TC to select the best interpolation method.

7

Direct Digital Synthesizer based on Field Programmable Gate Array

Gasik K., Szplet R.

Measurement Automation Monitoring

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2017

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Vol. 63, No. 6

220--222

EN

We present the principle (Chapter 2), implementation (Chapter 3) and test results (Chapter 4) of direct digital synthesizer (DDS) that most modules, i.e. phase accumulator, ROM memory and optional amplitude control module are implemented in a digital Field Programmable Gate Array (FPGA) device. To obtain smooth shape of analog output signals the FPGA device is followed by a digital-to-analog converter (DAC) and low-pass filter (LPF). The developed DDS allows for generating signals with frequency up to 50 MHz and amplitude up to 1 Vpp. The frequency adjustment resolution is 1.9 kHz, while the amplitude adjustment step equals 61.04 µV. The use of programmable device allows for changing the size of tuning words to adapt the DDS parameters to requirements of particular application.

8

Measurement subsystem for evaluation of local atomic clocks quality

Szplet R., Jachna Z., Różyc K., Kwiatkowski P.

Przegląd Elektrotechniczny

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2016

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R. 92, nr 11

39--42

EN

We present the design, implementation and test results of a new measurement system for continuous evaluation of atomic clocks quality and selection of the best one as a local reference clock that operation is coordinated with the governmental time scale created in National Metrology Institute. The described system is developed as a part of the project called Legal Time Distribution System performed within European program EUREKA.

PL

W artykule opisane są projekt, sposób realizacji oraz wyniki badań eksperymentalnych systemu pomiarowego do ciągłej ewaluacji jakości atomowych źródeł zegarowych i wyboru źródła referencyjnego, którego działanie jest koordynowane z urzędową skalą czasu. Opisany system został opracowany jako część projektu System Dystrybucji Czasu Urzędowego realizowanego w ramach europejskiego programu EUREKA.

9

Pseudo-random bit generators based on linear-feedback shift registers in a programmable device

Parol M., Dąbal P., Szplet R.

Measurement Automation Monitoring

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2016

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Vol. 62, No. 6

184--186

EN

We present the results of comparative study on three pseudo-random bit generators (PRBG) based on various use of linear-feedback shift registers (LFSR). The project was focused on implementation and tests of three such PRBG in programmable device Spartan 6, Xilinx. Tests of the designed PRBGs were performed with the use of standard statistical tests NIST SP800-22.

10

Time interval measurement module implemented in SoC FPGA device

Grzęda G., Szplet R.

International Journal of Electronics and Telecommunications

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2016

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Vol. 62, No. 3

237--246

EN

We presents the design and test results of a picosecond-precision time interval measurement module, integrated as a System-on-Chip in an FPGA device. Implementing a complete measurement instrument of a high precision in one chip with the processing unit gives an opportunity to cut down the size of the final product and to lower its cost. Such approach challenges the constructor with several design issues, like reduction of voltage noise, propagating through power lines common for the instrument and processing unit, or establishing buses efficient enough to transport mass measurement data. The general concept of the system, design hierarchy, detailed hardware and software solutions are presented in this article. Also, system test results are depicted with comparison to traditional ways of building a measurement instrument.

11

Parallel data processing in a 3-channel integrated time-interval counter

Jachna Z., Szplet R., Kwiatkowski P., Różyc K.

Measurement Automation Monitoring

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2015

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Vol. 61, No. 7

308--310

EN

In this paper, we discuss an issue of parallel data processing in multichannel time interval counters (TICs). Particularly we analyze this problem within the framework of a 3-channel TIC developed for the international project Legal Time Distribution System (LTDS). The TIC provides the high measurement precision (< 15 ps) and wide range (> 1s) that are obtained by combining reference clock period counting with in-period interpolation. A measurement process consists of three main stages: (1) events registration, (2) data processing and (3) data transfer. In the event registration stage all input events are identified and registered with related unique timestamps based on a consistent time scale. To achieve high measurement precision, the stream of timestamps is then processed using actual transfer characteristics of the TIC and offset values of all measurement channels. We describe the concept of parallel data processing and its implementation in a Spartan-6 FPGA device (XC6SLX75, Xilinx).

12

An autonomous microcontroller system for controlling a multi-channel time counter

Sondej D., Sawicki M., Szplet R.

Measurement Automation Monitoring

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2015

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Vol. 61, No. 7

305--307

EN

The paper presents the design of a microprocessor system intended for control, data processing and communication in a multi-channel time counter. The time counter is a relatively complex autonomous instrument designed for measurements of time with picosecond precision and frequency within a range of 3.5 GHz. The device employs a high-speed, single-chip microcontroller with event-driven programming without the mediation of an operating system. The autonomous operation of the measurement system with real-time controlling and data processing was achieved. The paper focuses on the hardware design and the software development model which enables collision-free and concurrent work of many components. The device uses advanced mechanisms available in STM32 series microcontrollers, allowing the efficient support for USB and Ethernet interfaces. The microprocessor system works at a relatively low frequency, which minimizes emission of interference and allows measuring time intervals with a high precision.

13

A study of the effect of temperature changes on the interpolating time counter

Sondej D., Szplet R.

Measurement Automation Monitoring

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2015

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Vol. 61, No. 7

302--304

EN

This paper presents an analysis of the impact of ambient temperature changes on main parameters of the interpolating time counter. The performed tests reveal that a relatively small change in the ambient temperature of 1°C causes a measurement error of the counter as large as 3.5 ps. The thorough research of two stages of interpolation of the counter allowed determining the main sources of the error. One of them is the temperature drift of widths of four-phase clock (FPC) segments in the first interpolation stage (FIS). It equals 2.5 ps/°C. The widths of FPC phases directly influence the active range of the second interpolation stage (SIS) and its offset. The test results also show that the temperature drift of the offset has a greater impact on the measurement accuracy than the temperature-driven changes of quantization steps in SIS. The presented conclusions are the first step to develop a new method for reducing the impact of changes in the ambient temperature on the measurement accuracy of the interpolating time counter.

14

A programmable delay line

Perko K., Szplet R.

Measurement Automation Monitoring

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2015

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Vol. 61, No. 7

311--313

EN

The paper describes the design and test results of a programmable digital delay line implemented in an FPGA device (Kintex-7, Xilinx). The operation of the delay line is based on the modified dual interpolation Nutt method that combines two actions, i.e.: (1) counting the periods of a reference clock and (2) time interpolating within a single clock period. The first action provides an extremely wide range of the introduced delays (> 9 minutes), while the second one allows reaching relatively high delay resolution (2 ns) with a timing jitter as low as 35 ps (until delay of 1 μs). The high metrological parameters of the designed delay line are achieved at the expense of increased difficulty in implementation of the method in an integrated circuit. The major problems to be solved were the synchronizations of input signals as well as synchronous and asynchronous parts of the system, which were effectively provided with the use of two dual-edge synchronizers, a clock signal logic level detection system and associated synchronizers.

15

A multichannel programmable distribution amplifier

Różyc K., Kwiatkowski P., Sawicki M., Jachna Z., Szplet R.

Measurement Automation Monitoring

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2015

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Vol. 61, No. 7

314--316

EN

This paper presents the design, operation and test results of a multichannel programmable distribution amplifier. The distributor is based on a reprogrammable device Spartan-6 FPGA (Xilinx) and is intended to distribute a 10 MHz or 5 MHz frequency reference signal as well as 1 PPS pulses. It is built in a 2U, 19” rack-mount enclosure and is equipped with a single optical and seven electrical inputs, as well as two optical and fourteen electrical outputs The transition time and additive jitter of the distribution amplifier were tested and they did not exceed 14 ns and 4.5 ps RMS (for electrical inputs/outputs), respectively. In the case of optical input/outputs, the results depend on the parameters of converters involved. The values of delays and jitter introduced by the distributor are slightly larger than for dedicated integrated circuits, but the advantage of this solution is the possibility to build signal distributors with a larger number of inputs/outputs and the ease to modify and meet requirements of various applications.

16

A hardware/software development environment for SoC-based time interval counters

Grzęda G., Szplet R.

Measurement Automation Monitoring

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2015

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Vol. 61, No. 7

299--301

EN

The paper describes a design environment for development of precise time counters. The design was implemented in a System-on-Chip Zynq from Xilinx as an embedded solution with a custom user interface. The paper presents the system design, a dedicated time counter interface, and software running on the processing part of the Zynq device. It also contains the results of all system performance tests. The tests reveal the design advantages over the traditional approach, involving an FPGA device connected to a PC that serves as a host with a dedicated user interface. The presented development environment allowed reducing the calibration and measurement times twofold and threefold, respectively. Furthermore, thanks to the bus interface designed for data transmission from the time counter to the control module, the 200 MB/s data throughput inside the SoC was achieved.

17

Wielokanałowy modułowy licznik czasu z użyciem układów programowalnych

Różyc K., Szplet R., Kwiatkowski P., Sawicki M., Jachna Z.

Pomiary Automatyka Kontrola

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2014

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R. 60, nr 7

432--434

PL

Przedstawiono budowę, zasadę działania i wyniki badań wielokanałowego modułowego licznika czasu. Umożliwia on równoczesny pomiar relacji czasowych pomiędzy impulsami wejściowymi (START), pochodzącymi z maksymalnie sześciu niezależnych źródeł zegarowych, a wspólnym dla wszystkich kanałów impulsem odniesienia (STOP). Moduły pomiarowe licznika wykonano z użyciem układów programowalnych FPGA Spartan-3 (Xilinx). Licznik charakteryzuje się zakresem pomiarowym do 1 s oraz precyzją pomiarów nie gorszą niż 250 ps.

EN

We present the design, operation and test results of a modular multichannel time counter built with the use of programmable devices. Its resolution is below 50 ps and the measurement range reaches 1 sec. The design of the counter is shown in Fig. 1. It consists of six independent measurement modules. Each measurement module contains a 2-channel time interval counter (Fig. 2) implemented in a general-purpose reprogrammable device Spartan-3 (Xilinx). To obtain both high precision and wide measurement range, the counting of periods of a reference clock is combined with a two-stage interpolation within a single period of the clock signal [6]. The interpolation involves a four-phase clock in the first interpolation stage [8] and a time delay coding line in the second interpolation stage. The reference clock module contains an integrated digital synthesizer [7], that provides the reference clock signal of 250 MHz for measurement modules, and is driven by an external clock source of 5 MHz or 10 MHz. The standard measurement uncertainty of the time counter was tested (Figs. 3 and 4) carefully and it did not exceed 250 ps in the full measurement range. As the acid test of the time counter, the differences between signals of 1 PPS from the tested clock sources and the reference 1 PPS signal were also verified (Figs. 5 and 6). The modular design makes the multi-channel time counter easy to modify to meet requirements of various applications.

18

Scalony licznik czasu z użyciem stempli czasowych i interpolacji dwustopniowej

Kwiatkowski P., Szplet R., Jachna Z., Różyc K.

Pomiary Automatyka Kontrola

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2014

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R. 60, nr 7

435--437

PL

W artykule opisano budowę i działanie licznika czasu opartego na metodzie stempli czasowych i dwustopniowej interpolacji. Licznik został zaimplementowany w układzie programowalnym FPGA Kintex-7 firmy Xilinx. Pokazano sposób tworzenia stempli czasowych o wysokiej rozdzielczości oraz opisano problemy projektowe pojawiające się podczas implementacji projektu w układzie FPGA. Opracowany licznik charakteryzuje się wysoką rozdzielczością (< 11,6 ps) i precyzją (< 12 ps) oraz dużą szybkością powtarzania pomiarów (do 12 milionów pomiarów na sekundę). Słowa kluczowe: układy programowalne, przetworniki czasowo-cyfrowe, metoda stempli czasowych, interpolacja dwustopniowa.

EN

This paper presents an integrated time counter based on timestamps and two-stage interpolation methods implemented in an FPGA programmable device. The timestamps method [2, 3] is useful, among others, in physical experiments and laser ranging systems [2, 4, 5]. To obtain high (picoseconds) resolution, it can be combined with the Nutt interpolation method [1, 6]. The principle of measurement is described in Section 2 and shown in Fig. 1. The time counter contains a period counter, a period counter register and 8 independent channels (Fig. 2, Section 3). Each channel consists of a multiphase clock generator, first and second interpolation stage modules and a channel register. The principle of operation and the way of implementing them in a Kintex-7 FPGA device (Xilinx) [7] are also presented in Section 3. The time counter was examined in terms of resolution and precision for each measurement channel (Section 4). The resolution was evaluated using the statistical code density test [8] and its value was below 12 ps. In Fig. 3 there is shown the time counter precision. In the range up to 1 ms it does not exceed 12 ps. For longer time intervals the precision is worsened by the limited stability of the reference clock. The maximum measurement rate for a single channel was experimentally estimated as 12 million measurements per second. The presented time counter is characterized by high metrological parameters (due to the interpolation method) and wide functionality (due to the time stamps).

19

Procesor kodu do realizacji procedur kalibracyjnych w interpolacyjnym liczniku czasu

Jachna Z., Szplet R., Kwiatkowski P., Różyc K.

Pomiary Automatyka Kontrola

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2014

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R. 60, nr 7

438--440

PL

W artykule opisano projekt procesora kodu (PK) stanowiącego fragment dwukanałowego precyzyjnego licznika czasu z niezależnymi interpolatorami dwustopniowymi. Projekt został zrealizowany w układzie programowalnym XC6SLX75 (Xilinx). Zadaniem układów PK jest wykonywanie kalibracji linii kodujących, w wyniku której następuje aktualizowanie charakterystyk przetwarzania i w efekcie zwiększenie precyzji pomiarowej licznika. Dzięki sprzętowej implementacji algorytmów kalibracyjnych uzyskuje się skrócenie czasu wykonywania kalibracji, zmniejszenie liczby danych przesyłanych do komputera oraz zmniejszenie złożoności oprogramowania sterującego.

EN

In the paper there is presented a design of a code processor (PK) as a part of a 2-channel precise time counter with independent 2-stage interpolators. The project was implemented in Spartan-6 (Xilinx) FPGA device. The main task of the PK is calibration of coding lines, resulting in updating transfer characteristics and, as an effect, higher measurement precision of the counter. Thanks to the hardware implementation of calibration algorithms there are achieved: the shorter execution time of calibration procedures, the lower amount of data transferred into the computer and less complex control software. The first simple realization of the PK has been implemented using Spartan-3 device (Xilinx) [8]. This paper presents a new, improved realization of the PK whose characteristic is more suited for the newest counters and those to be invented in the future. The use of VHDL language for description of the PK makes it more susceptible to be adapted. This paper consists of description of the counter with advanced architecture of interpolators [7] , where 10 independent time coding lines where implemented in each measurement channel. The operating principle of the PK is described based on the following scheme: precise description of code density test realization, the way of forming the transfer characteristic and the results calculations.

20

Oprogramowanie diagnostyczno-sterujące interpolacyjnego licznika czasu w układzie programowalnym

Grzęda G., Sondej D., Szplet R.

Pomiary Automatyka Kontrola

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2014

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R. 60, nr 7

441--443

PL

W artykule opisano projekt oprogramowania diagnostyczno-sterującego licznika czasu z kodowaniem wielokrotnym w niezależnych liniach kodujących, wykonanego w układzie programowalnym Spartan-6 firmy Xilinx. Przedstawiono sposób sterowania licznikiem czasu, koncepcję oprogramowania sterującego, jego zadania oraz warstwową budowę. Opisano graficzny interfejs użytkownika programu i jego funkcjonalność. Prezentowane są także wyniki badań eksperymentalnych licznika czasu.

EN

This paper presents the diagnostic and control software of a time interval counter with multi-edge coding in independent coding lines, implemented in the Spartan-6 FPGA device manufactured by Xilinx. The method of time-to-digital conversion [1] is presented along with the design of the time interval counter (Fig. 1). Subsequently, the main goals of the control software, along with its logical structure, are described. The paper shows the layer model (Fig. 2) of the program, reveals the method of communication with the time counter and the way of decoding measurement frames. The bottom-most communication layer transfers the data through USB to the device. The next control layer operates on hardware registers and the measurement layer calibrates the counter and triggers measurements. Finally, the graphic user interface (GUI) layer binds the application together and steers the user interface. The program operates in two main modes: calibration and time interval measurement. Apart from both these modes, the data flow across the layers and the way of saving data generated during counter operation are described. The GUI (Fig. 3) is described as well, showing the main types of operation along with the capabilities of configuring the calibration and measurement processes. Finally, the paper presents the test results of the time counter in both main operation modes (Fig. 4).