In the paper, we report on ways to optimize metal-ferroelectric-insulator-semiconductor (MFIS) stacks in terms of the thickness combination of the ferroelectric and the buffering insulator layers in order to reduce the operation voltage of MFIS based non-volatile memory elements. The stack contains poly(vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)) as a ferroelectric layer. We discuss the optimization of the deposition of this material in order to produce thin films with high polarization. This must be accompanied by an adapted buffer layer, where reduction of thickness as well as increase of permittivity can be taken into account. We show the results based on capacitance voltage measurements (CV) on MFIS stacks, where SiO2 and Al2O3of different thicknesses have been used. Furthermore, we perform simulations of the CV characteristics and we are able to quantify the polarization and decline it from the CV curves. We observe for a 120 nm P(VDF-TrFE)/11 nm Al2O3 stack in a š20V CV loop almost saturated polarization values as predicted by the simulations in that way.
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