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Inﬂuence of substrate meshing on the accuracy of EPFL substrate model for smart power ICs

Stefanucci C, Buccella P, Kayal M., Sallese J.M.

International Journal of Microelectronics and Computer Science

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2014

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Vol. 5, nr 2

61--68

EN

Minority carriers diffusion in Smart Power ICs substrate can be simulated in standard spice-like software using the EPFL Substrate Model. This model is based on a parasitic substrate network extracted from the integrated circuit layout following a given meshing strategy. In this work Design of Experiments (DOE) techniques are used to run a limited number of simulations to evaluate the inﬂuence of the meshing strategy on the accuracy of the model when compared to Technology Computer Aided Design (TCAD) simulations. A parasitic lateral BJT will be analyzed as two-dimensional case study with both spice-like and ﬁnite element simulations for the minority carriers diffusion. Using statistical analysis a linear model is developed to discover the main geometrical domains inﬂuencing the accuracy of the studied model.

2

Extraction of an equivalent electrical circuit for SPICE simulation of substrate minority carriers propagation

Buccella P, Stefanucci C, Sallese J.M., Kayal M.

International Journal of Microelectronics and Computer Science

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2014

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Vol. 5, nr 2

47--53

EN

This paper presents an equivalent electrical circuit for substrate minority carriers SPICE simulation. The electrical circuit parameters are extracted from substrate meshing applying the ﬁnite difference method. This model is derived from a linearization of drift-diffusion equations and not from the closed form solution. Further, the proposed circuit is solved with available SPICE simulators because of electrical analogies with physical quantities. As a result, the minority carrier diffusion current is included automatically in the total substrate current computation. SPICE simulation results are compared with device simulator results for the one and three-dimensional cases.

3

Offset Drift Dependence of Hall Cells with their Designed Geometry

Paun M. A., Sallese J. M., Kayal M.

International Journal of Electronics and Telecommunications

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2013

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Vol. 59, No. 2

169-175

EN

In this paper, the performance of CMOS Hall Effect Sensors with four different geometries has been experimentally studied. Using a characteristic measurement system, the cells residual offset and its temperature behavior were determined. The offset, offset drift and sensitivity are quantities that were computed to determine the sensors performance. The temperature coefficient of specific parameters such as individual, residua offset and resistance has been also investigated. Therefore the optimum cell to fit the best in the performance specifications was identified. The variety of tested shapes ensures a good analysis on how the sensors performance changes with geometry.

4

Compact Modelling of Ultra Deep Submicron CMOS Devices

Grabiński W., Sallese J.M., Bucher M., Krummenacher F.

Bulletin of the Polish Academy of Sciences. Technical Sciences

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2002

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Vol. 50, Nr 1

13--27

EN

The technology of CMOS very large-scale integrated circuits (VLSI) has achieved remarkable advances over last 25 years and the progress is expected to continue well into this century. However, even before the minimum feature sizes of the active VLSI devices reach the fundamental limits, this evolution is expected to encounter severe technological and economic problems when the dimensions go below sub-quarter micron, the so called ultra deep submicron (UDSM). There are many physical effects that need to be addressed while modelling UDSM devices , such as quantization of the inversion layer, mobility degradation, carrier velocity saturation and overshoot, polydepletion effects. In this paper, the advances in compact MOSFET devices will be illustrated using application examples of the EPEL-EKV model.