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Content available Optimized implementation of lattice Boltzmann method in ARUZ
Jabłoński Grzegorz, Kupis Joanna
International Journal of Microelectronics and Computer Science
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2018
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Vol. 9, nr 2
79--84
EN
The paper presents the optimized implementation of the Lattice Boltzmann method on ARUZ, a massively parallel FPGA-based simulator located in Lodz, Poland. Compared to previous publications, a performance improvement of 46% has been achieved on D2Q9 lattice due to overlapping of communication with computation. The presented approach is suitable also for other cellular automata-based simulations. Extrapolation of results from the single ARUZ board suggests, that LBM simulation of 1080 × 480 lattice on 18 panels of ARUZ would reach the performance of 302 · 103 MLUPS (Million Lattice Updates per Second). This implementation has been compared to the classical supercomputer solution, giving much better power efficiency (3000 MLUPS/kW vs. 1280 MLUPS/kW, respectively).
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