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Study of Capacitor & Diode Aging effects on Output Ripple in Voltage Regulators and Prognostic Detection of Failure

Preethi Sharma K., VijayaKumar T.

International Journal of Electronics and Telecommunications

2022

Vol. 68, No. 2

281--286

Objectives: To design and simulate a buck converter and detector circuit which can prognostically indicate the power supply failure. Failure of Aluminium Electrolytic Capacitor (AEC) is considered as the parameter causing the power supply failure. To analyse variation of output ripple voltage due to possible changes in the Equivalent Series Resistance (ESR) and effective capacitance of the capacitor and design a detector to detect the failure of power supply prognostically. Methods: A DC-DC buck converter in SMPS topology is designed by assuming an input voltage of 12V with 3 volts possible fluctuations and an output voltage of 3.3 volts is desired. Simulation is carried out to measure the variation in output ripple voltage caused due to aging of electrolytic capacitor using TINA by Texas Instruments. A detector is also designed to compare the ripple voltage and a predefined threshold voltage so as to indicate the possible failure of Switched Mode Power Supply (SMPS) well in advance by monitoring the output ripple increase. Novelty: Having a fault tolerant power supply is very important in safety critical applications. Here by monitoring the output ripple variation, the degradation of AEC is predicted by calculating the ESR and capacitance variation. This simple yet effective prognostic detection will support in the design of fault tolerant power supplies. Highlight: It is found that, the ripple at the output increases with aging of the electrolytic capacitor, as with time the equivalent capacitance decreases and Equivalent Series Resistance (ESR) of the capacitor increases. The designed detector output is found to prognostically indicate the failure of SMPS.

Effect of DC Capacitor Size on D-STATCOM Voltage Regulation Performance Evaluation

Hannan M. A.

Przegląd Elektrotechniczny

2012

R. 88, nr 12a

243-246

This paper describes the modelling and simulation of distribution static compensator (D-STATCOM) focused with effect of DC capacitor size and voltage regulation. Different capacitor values have been investigated to reduce the load ripple voltage during the charging and discharging of the capacitor. The optimum capacitor valuse has been determined to obtained the lowest ripple voltage within the rage of 8%. Capacitive and inductive mode of D-STATCOM operation have been also investigated and obtained results proved that the capability of the D-STATCOM in regulating the system voltage is near to the rated value of 1.0 p.u.

W artykule przedstawiono sposób budowy modelu i symulacje kompensatora pasywnego D-STATCOM, ze naciskiem na analizę wpływu pojemności kondensatorów oraz regulacji napięcia na jego działanie. Badania wykonano dla różnych pojemności i wyznaczono optymalną, zapewniającą najmniejsze wahania napięcia (w zakresie 8%). Analizie poddano działanie kompensatora przy charakterze pojemnościowym i indukcyjnym.