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Ultra Low Power Design for Digital CMOS Circuits Operating Near Threshold

Kalra S., Bhattacharyya A. B.

International Journal of Electronics and Telecommunications

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2017

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Vol. 63, No. 4

369--374

EN

Circuits operating in the subthreshold region are synonymous to low energy operation. However, the penalty in performance is colossal. In this paper, we investigate how designing in moderate inversion region recuperates some of that lost performance, while remaining very near to the minimum energy point. An α power based minimum energy delay modeling that is continuous over the weak, moderate, and strong inversion regions is presented. The value of α is obtained through interpolation following EKV model. The effect of supply voltage and device sizing on the minimum energy and performance is determined. The proposed model is utilized to design a temperature to time generator at 32nm technology node as the application of the proposed model. The abstract goes here.

2

Selected hardware solutions used in the process of monitoring bioparameters

Michnik A., Szczurek Z., Szuster B., Kubik B., Kowalski P.

International Journal of Microelectronics and Computer Science

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2016

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Vol. 7, nr 1

26--32

EN

The paper presents the idea behind the implementation of a system designed to monitor biomedical parameters and the subject's behaviour on the basis of the architecture of measurement modules located on the body. The system was developed as a result of market launch of new generations of electronic devices combining high functionality, small size and low power consumption. The paper presents the elements of the system called BioSip, along with hardware solutions selected for the objectives to be accomplished, i.e. providing communication between system elements that would be efficient and resistant to artefacts, extending the time of operation for battery power supply, as well as ensuring a satisfactory level of reliability and ease of use.

3

A 400 fJ per-cycle frequency reference for internet of things

Coustans M., Krummenacher F., Terrier C., Kayal M.

International Journal of Microelectronics and Computer Science

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2016

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Vol. 7, nr 2

41--46

EN

This work presents an ultra-low power oscillator designed to target different contexts, such as crystal-assisted timekeeping, reference oscillator to optimize the always on domain of a microcontroller or wake-up timer. This oscillator enables ultralow power operation in 0.18 μm CMOS technology; the core oscillator consumes 2.5 nW at room temperature, with a temperature stability of 14 ppm/°C [-40°C - 60°C] and 0.07 %/V supply sensitivity.

4

Design of an Ultra-Low Power CT Σ∆ A/D Modulator in 65nm CMOS for Cardiac Pacemakers: From System Synthesis to Circuit Implementation

Wang Y., Cai H.

International Journal of Electronics and Telecommunications

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2014

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Vol. 60, No. 1

109-115

EN

A high performance, ultra-low power, fully differentia 2nd-order continuous-time Σ∆ analogue-to-digital modulator for cardiac pacemakers is presented in this paper. The entire design procedure is described in detail from the high-level system synthesis in both discrete and continuous-time domain, to the low-level circuit implementation of key functional blocks of the modulator. The power consumption of the designed modulator is rated at 182nA from a 1.2V power supply, meeting the ultra-low power requirement of the cardiac pacemaker applications. A 65nm CMOS technology is employed to implement the Σ∆ modulator. The modulator achieves a simulated SNR of 53.8dB over a 400 Hz signal bandwidth, with 32KHz sampling frequency and an oversampling ratio of 40. The active area of the modulator is 0.45×0.50mm².