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Design of a 3.3V Four-Quadrant Analog CMOS Multiplier

Szczepański S., Kozieł S.

Bulletin of the Polish Academy of Sciences. Technical Sciences

2003

Vol. 51, nr 2

163-172

The two CMOS four-quadrant analog multipliers that can operate from a supply voltage of 3.3V are presented. The proposed circuit technique has been developed using MOS transistors working both in saturation and nonsaturation regions. Simulation results have shown that the introduced circuit based on MOS devices operating in the linear region has the total harmonic distortion (THD) less than 0.75% for input signal up to 2Vpp with 10MHz sine wave. A 3-dB bandwidth about 1GHz is attainable from either input. A power consumption of the circuit is 1.4mW.