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Concurrent operation of processors in the bit-byte CPU of a PLC

Chmiel M., Hrynkiewicz E.

Control and Cybernetics

2010

Vol. 39, no 2

559-579

The paper presents some selected hardware solutions for the PLC dual processor bit-byte CPUs, which are oriented at optimised data exchange between the CPU processors. The optimisation aims at maximum utilisation of capabilities of the two-processor architecture of the CPU. The key point is preserving high speed of instruction processing by the bit-processor, and high functionality of the byte-processor. The structure should enable the processors to work in concurrent mode as far as it is possible, and minimise the situations, when one processor has to wait for the other.

Fast Operating PLC Based on Event-Driven Control Program Tasks Execution

Chmiel M., Hryniewicz E., Milik A.

Electronics and Telecommunications Quarterly

2009

Vol. 55, No 2

269-286

The paper presents modified idea of program execution in PLCs. Instead of serial cyclic execution of control program event-driven execution is proposed. Suggested approach to program execution allows for selective execution of program parts or tasks. Only these blocks from entire program are executed whose variables have changed since last calculation. Proposed method can be implemented as software modification or as hardware accelerated solution. The most important part of the idea is task or subprogram triggering condition computation. Methods of program optimization are discussed. In order to determine program blocks that require recalculation in current program scan execution specific hardware support is planned to be researched. Memory content change detection unit allows to determine changes in memory content since last program block execution.

On reducing PLC response time

Chmiel M.

Bulletin of the Polish Academy of Sciences. Technical Sciences

2008

Vol. 56, nr 3

229-238

The dual core bit-byte CPU must be equipped with properly designed circuits, providing interface between the two processor units, and making it possible to exploit all its advantages like versatility of the byte unit and speed of the bit unit. First of all, the interface circuits should be designed in such a way, that they don't disturb maximally parallel operation of the units, and that the CPU as a whole works in the same manner as in a standard PLC. The paper presents hardware solutions supporting effective operation of PLC CPU-so Possibilities of solving problems concerning data exchange between a CPU and peripheral circuits were presented, with a special stress on timers and counters, and also on data exchange between the bit unit and the byte unit. The objective of the proposed solutions is to decrease the time necessary for a CPU to access its peripheries.