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1

An Enhanced IEEE1588 Clock Synchronization for Link Delays Based on a System-on-Chip Platform

Wei Xiaohan, Xiong Xingzhong, Luo Zhongqiang, Wang Jianwu, Cheng Kaixing

International Journal of Electronics and Telecommunications

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2021

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Vol. 67, No. 2

289--294

EN

The clock synchronization is considered as a key technology in the time-sensitive networking (TSN) of 5G fronthaul. This paper proposes a clock synchronization enhancement method to optimize the link delays, in order to improve synchronization accuracy. First, all the synchronization dates are filtered twice to get the good calculation results in the processor, and then FPGA adjust the timer on the slave side to complete clock synchronization. This method is implemented by Xilinx Zynq UltraScale+ MPSoC (multiprocessor system-on-chip), using FPGA+ARM software and hardware co-design platform. The master and slave output Pulse Per-Second signals (PPS). The synchronization accuracy was evaluated by measuring the time offset between PPS signals. Contraposing the TSN, this paper compares the performance of the proposed scheme with some previous methods to show the efficacy of the proposed work. The results show that the slave clock of proposed method is synchronized with the master clock, leading to better robustness and significant improvement in accuracy, with time offset within the range of 40 nanoseconds. This method can be applied to the time synchronization of the 5G open fronthaul network and meets some special service needs in 5G communication.

2

FPGA based real-time epileptic seizure prediction system

Cosgun Ercan, Çelebi Anil

Biocybernetics and Biomedical Engineering

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2021

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Vol. 41, no. 1

278--292

EN

The development of systems that can predict epileptic seizures in real-time offers great hope for epilepsy patients. These systems aim to prevent accidents that patients may experience caused by the loss of consciousness during seizures. Therefore, patients must use real-time epileptic seizure prediction systems that do not interfere with their daily activities. In this study, using the unipolar EEG data from a surface electrode, a patient-specific estimation system is implemented in real-time on a system on chip (SoC) that contains an embedded processor and programmable logic blocks. The European epilepsy database EPILEPSIAE is used in the scope of this work. In the proposed system, pre-processing is applied to the EEG data. Then, the features of the data in the frequency domain are extracted. The classifier model is trained with the RusBoosted Tree cluster classifier, which is a machine learning algorithm. Testing is carried out using the proposed classification model. Threshold values are determined, and then false alarms and erroneous classifications are prevented by post-processing. At the end of the tests, prediction success, sensitivity (SEN), Specificity (SPE), False Prediction Rate (FPR), and prediction times are obtained as 77.30%, 95.94%, 0.041 h_1, and 33.23 min, respectively. The proposed system outperforms other studies in the liter-ature in the number of electrodes, real-time operation, hardware/software architecture, and FPR performance. A wearable seizure prediction system seems to be commercialized according to the results achieved in this study.

3

Testbed for thermal and performance analysis in MPSoC systems

Sojka Michal, Benedikt Ondřej, Hanzálek Zdeněk, Zaykov Pavel

Annals of Computer Science and Information Systems

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2020

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Vol. 21

683--692

EN

Many modern computing platforms in the safety-critical domains are based on heterogeneous Multiprocessor System-on-Chip (MPSoC). Such computing platforms are expected to guarantee high-performance within a strict thermal envelope. This paper introduces a testbed for thermal and performance analysis. The testbed allows the users to develop advanced scheduling and resource allocation techniques aiming at finding an optimal trade-off between the peak temperature and the achieved performance. This paper presents a new, open-source Thermobench tool for data collection and analysis of user-defined workloads. Furthermore, a methodology for shortening the time needed for the data collection is proposed. Experiments show that a significant amount of time can be saved. Specifically, time reduction from 60 minutes to 15 minutes is achieved with the i.MX8 MPSoC from NXP while running a set of user-defined benchmarks that stress CPU, GPU, and different levels of the memory hierarchy.

4

A Method to Support Diagnostics of Dynamic Faults in Networks of Interconnections

Garbolino T.

International Journal of Electronics and Telecommunications

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2018

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Vol. 64, No. 3

407--420

EN

The article is devoted to the method facilitating the diagnostics of dynamic faults in networks of interconnection in systems-on-chips. It shows how to reconstruct the erroneous test response sequence coming from the faulty connection based on the set of signatures obtained as a result of multiple compaction of this sequence in the MISR register with programmable feedback. The Chinese reminder theorem is used for this purpose. The article analyzes in detail the various hardware realizations of the discussed method. The testing time associated with each proposed solution was also estimated. Presented method can be used with any type of test sequence and test pattern generator. It is also easily scalable to any number of nets in the network of interconnections. Moreover, it supports finding a trade-off between area overhead and testing time.

5

Pipelined pseudo-random number generator with the efficient post-processing method

Dąbal P.

International Journal of Microelectronics and Computer Science

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2015

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Vol. 6, nr 2

43--48

EN

This brief proposes a novel architecture of the chaotic pseudo-random bit generators (PRBGs) based on the chaotic nonlinear model and pipelined data processing. We investigated PRBG built on the chaotic logistic map and frequency dependent negative resistances (FDNR). A significant enhancement in terms of output throughput has been achieved by combining the advantages of pipelining with post-processing based on fast logical operations like bit shifting and XOR. The proposed method has been implemented using programmable SoC Zynq device from Xilinx. We verified output pseudo-random bit stream by standard statistical tests NIST SP800-22. We also present detailed comparison of the proposed post-processing method with the methods reported previously by the other authors. In particular, we compared the maximum output throughput and amount of total logical resources required by PRBG implementation in the programmable SoC device. For PRBGs based on the logistic chaotic map and frequency dependent negative resistance (FDNR) we obtained speed-up factors equal to 33% and 14%, respectively. By composing the output stream of 3 data channels in PRBG with FDNR element, we get the maximum throughput equal to 38.43 Gbps. That is significantly greater comparing to the chaotic PRBGs described so far.

6

Hardware Design of Image Channel Denoiser for FPGA Embedded Systems

Sharifi-Tehrani O.

Przegląd Elektrotechniczny

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2012

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R. 88, nr 3b

165-167

EN

In this article an FPGA-based image channel denoiser using a 1D-standard-LMS algorithm is proposed. The designed core is written in VHDL93 language as basis of 1D-FIR adaptive filter. The proposed core is FPGA-brand-independent, hence can be ported on any brand to create a system-on-chip (SoC). Although using a pure-hardware implementation results in better performance, it is more complex than other structures such as digital signal processors and Hardware/Software co-designs. The results show improvements in area-resource utilization and convergence speed in the designed pure-hardware channel denoiser core.

PL

Zaproponowano metodę usuwania szumów w systemie FPGA bazującą na algorytmie LMS i 1D-SOI filtrze adapatacyjnym. Przedstawiono możliwości zastosowania metody a gotowym układzie zintegrowanym.

7

System typu SoC do kryptoanalizy szyfrów opartych na krzywych eliptycznych

Orkiszewski M., Wojciechowski T., Rawski M.

Pomiary Automatyka Kontrola

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2010

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R. 56, nr 7

745-748

PL

W pracy zaprezentowano system typu SoC (System-on-Chip) zrealizowany w układach FPGA wspomagający obliczenia pozwalające na złamanie szyfru opartego na krzywych eliptycznych. Do ataku kryptoanalitycznego wykorzystano algorytm rho Pollarda. System zbudowany jest ze sprzętowych jednostek obliczeniowych HardRho pracujących pod kontrolą procesora NiosII i wykorzystuje interfejs Ethernet do komunikacji zewnętrznej. Omówiona została koncepcja budowy rozproszonego systemu obliczeniowego składającego się z jednostek obliczeniowych będących systemami typu SoC.

EN

Public-key cryptosystems allow secure connections and data exchange through unsafe communication channel without the need of a previous secure key exchange. One of popular cryptosystems used nowadays is Elliptic Curve Cryptosystems (ECC). Cryptanalytic attack on ECC system involves solving the Elliptic Curve Discrete Logarithm Prob-lem (ECDLP). The best known algorithm used to solve ECDLP is Pollard's rho method. So far successful attacks on ECC systems have mostly been based on distributed computer networks. In this paper a hardware cryptanalytic system is presented. The system is implemented in FPGA devices and performs computations of rho Pollard's algorithm. System is based on SoC solution (System-on-Chip) and works under control of a central server in order to form a greater distributed computing system. In the first paragraph of this paper there are presented the aim of work as well as the reasons for choosing FPGA devices and SoC solution. The second paragraph gives the theoretical background [3, 4, 5], explains the basic terms and presents the rho Pollard's algorithm [6, 7]. The third paragraph describes HardRho computation unit HardRho hardware (Fig. 1) and shows differences between the current and recent unit version of unit described in [8, 9]). The fourth paragraph of the paper deals with the SoC solution composed of several HardRho units, NiosII processor and Ethernet communication interface. The system structure (Fig. 2) and internal components [11, 12] are presented. The fifth paragraph is nfocused on the results of implementation and the estimated time of cryptanalysis of an elliptic curve ECC2-89 [1] (Tab. 1). The HardRho unit and [13] are compared (Tab. 2). The obtained results suggest high efficiency of the presented SoC solution. The future investigations and possible optimisation of the system are discussed.

8

Ograniczenie mocy dynamicznej w architekturze sprzętowego kodera standardu JPEG2000

Modrzyk D.

Pomiary Automatyka Kontrola

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2010

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R. 56, nr 7

793-795

PL

W artykule przedstawiono ideę redukcji poboru mocy dynamicznej w złożonym układzie multimedialnym, jakim jest koder standardu JPEG2000. Idea ta opiera się na sterowaniu włączaniem i wyłączaniem sygnałów zegarowych dla odpowiednich bloków przetwarzających, za pomocą specjalizowanego modułu kontrolera mocy. Wykonane symulacje oraz analizy poboru mocy wskazują, że zastosowana metoda prowadzi do znacznej redukcji mocy dynamicznej, w porównaniu do oryginalnej architektury kodera.

EN

In this paper an idea of dynamic power reduction in a complex, hardware encoder of JPEG2000 standard is presented. The algorithm is based on clock gating technique. Due to sequential data flow in the encoder architecture, there are introduced clock signals, active only during computations in particular processing blocks. Switching the clock signals is performed by a specialised power manager module, instantiated at the chip level of the presented encoder. Clock signals are produced in the combinational logic, using flags from processing units that inform about compression phases in the encoder. Technology dependent clock buffers are used to eliminate "glitch" effect, during switching the clock signals. Power consumption in both, optimised and original, IP cores is measured using Xilinx XPower Analyzer 10.1, when taking into account switching activity obtained from gate level simulations of the design. The experimental results show that the proposed method leads to significant decrease in the dynamic power compared to the original encoder architecture. The described technique can be implemented in both FPGA and ASIC circuits.

9

Osobliwości stosowania arytmetyki ułamkowej w nowoczesnych układach FPGA

Maslennikow O., Ratuszniak P., Khadzynov W., Pawłowski P., Berezowski R., Sergiyenko A.

Elektronika : konstrukcje, technologie, zastosowania

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2008

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Vol. 49, nr 11

200-203

PL

W artykule przedstawiono wyniki badań dotyczących wyłonienia zalet i wad stosowania arytmetyki ułamkowej w jednostkach arytmetyczno-logicznych systemów jednoukładowych realizowanych w nowoczesnych układach FPGA. Krótki opis osobliwości stosowania arytmetyki ułamkowej, jak i opis jej zalet wykorzystują przedstawione w referacie porównanie parametrów modeli VHDL kilku potokowych bloków operacyjnych działających w tej arytmetyce z parametrami analogicznych bloków operacyjnych działających w arytmetyce stało- i zmiennoprzecinkowej, wygenerowanych przy użyciu oprogramowania Xilinx CORE Generator. Głównymi kryteriami porównania są złożoność sprzętowa układu, maksymalna częstotliwość jego działania oraz liczba stopni w potoku.

EN

In this paper, the most advantages of the rational fraction arithmetic (RFA) is selected, which are apeared in a case of implementation of RFA operation blocks (multipliers, dividers, etc.) and arithmetic-logic (ALU) units in the modern FPGA implementation. The comparison of the RFA blocks and units with the known ones operating with the fixed-point or float point data showed the lower hardware volume and higher throughput without decreasing of calculation precision. The VHDL modeling showed the possibility of use such data representation in solving linear equations by several different methods (for example Cholesky method), and showed the reducing of the hardware complexity of rational fraction ALU in everal times comparing with similar arithmetic units operating with float-point numbers (without decreasing of AU performance).

10

Algorytmy i metody dwuprocesorowego sterowania precyzyjnym licznikiem czasu

Sondej T., Gołaszewski M.

Biuletyn Wojskowej Akademii Technicznej

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2008

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Vol. 57, nr 4

309-326

PL

W artykule przedstawiono projekt oprogramowania systemu wieloprocesorowego, składającego się z dwóch procesorów programowych Nios II firmy Altera i precyzyjnego licznika czasu o rozdzielczości około 80 ps. Pierwszy procesor odpowiedzialny jest za komunikację systemu przez interfejs Ethernet z aplikacją uruchamianą na komputerze PC. Drugi procesor steruje licznikiem czasu oraz zajmuje się obliczeniami statystycznymi w czasie wykonywania próby pomiarowej. W artykule przedstawiono również opis projektu sprzętowego oraz problem komunikacji pomiędzy procesorami w systemie wieloprocesorowym.

EN

This paper presents issues of designing and implementing soft ware for multiprocessor systems. Practical example consists of two soft core processors Nios II from Altera. Developed system is designed for control and data processing of precision timer counter with 80-ps resolution. The first processor runs as a server, providing communication and supervision of the system via the Internet. The second processor controls timer counter and performs statistical computation. Shared memory from FPGA resources is used to interchange data between processors.

11

Ocena wydajności procesorów wbudowanych w układy FPGA

Sondej T., Zagoździński L., Pełka R.

Biuletyn Wojskowej Akademii Technicznej

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2006

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Vol. 55, nr sp.

27-42

PL

W artykule przedstawiono ocenę wydajności sprzętowego (PowerPC) i programowego (MicroBlaze) procesora, wbudowanego w układ FPGA typu Virtex-4 firmy Xilinx. Uzyskane miary wydajności zestawiono z wynikami uzyskanymi dla procesorów autonomicznych typu ARM i DSP. Opisane szczegółowe porównanie procesorów wbudowanych w układ FPGA może pomóc projektantowi w wyborze sprzętowego lub programowego procesora dla różnych aplikacji oraz daje ogólną ich ocenę w porównaniu z procesorami autonomicznymi. Badania wydajności przeprowadzono na dwa sposoby: pierwszy dotyczył testów dla jednakowej częstotliwości pracy zegara (100 MHz) i różnych konfiguracji pamięci, natomiast drugi przeprowadzono dla częstotliwości maksymalnych.

EN

This paper describes a simple, yet effective and convenient method for evaluation of the computing performance of hard- and soft-processor (PowerPC and Micro-Blaze, respectively) embedded in Virtex-4 FPGA from Xilinx. Experimental results have been compared with standalone ARM and DSP microprocessors. Detailed comparison of the performance of both processors is presented to help designers to choose between the hard- and soft-processor in different applications. This comparison has been performed in twofold way: the PowerPC and Micro-Blaze cores have been tested at the same clock frequency (100 MHz) for some available configurations of the memory subsystem, and maximum performance factors of both cores have been measured using maximum clock speed.