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The architecture of a low phase noise low power Delta-Sigma Fractional-N synthesizer

Siwiec Krzysztof, Pleskacz Witold A.

International Journal of Microelectronics and Computer Science

2018

Vol. 9, nr 4

161--166

In this paper a new Delta Sigma Fractional N synthesizer architecture is presented. The synthesizer achieves low fractional spurs and quantization noise, which relaxes the trade-off between PLL bandwidth and phase noise. The proposed architecture is based on two delay lines, which are used to compensate the phase error resulting from fractional synthesis. Additionally, dedicated control and calibration circuitry is described. The synthesizer has been implemented in standard 130 nm CMOS technology, occupies 0.1S4 mm² silicon area and dissipates 3.6 mW of power from 1.2 V supply. Measurements show that the presented architecture achieves 30 dB phase noise reduction in comparison with a standard Delta Sigma Fractional N synthesizer. The integrated rms jitter is 2.76 ps and worst case fractional spur is -52 dBc.

The Design of the Signal Generator Circuit for Single-Phase Industrial Frequency Power Based on XC2C64A

Xiao H., Lv K.

Przegląd Elektrotechniczny

2012

R. 88, nr 5b

76-78

The paper mainly introduces the new signal generator circuit of industrial frequency power based on XC2C64A, which focus all digital circuit in a CPLD chip, making simple structure and convenient debugging. And the general diagram, design idea, the benchmark waveform signal oscillating circuit, frequency synthesis circuit, phase synthesis circuit and D/A transformation circuit are given in the paper. The phase and frequency of the circuits are simulated.

Zaprezentowano nową koncepcję genertatora sygnałów o częstotliwości przemysłowej wykorzystujący syntezę częstotliwości i fazy oraz przetwornik cyfrowo-analogowy. Układ bazuje na obwodzie XC2C64A.

Application of Frequency Locked Loop in Consumption Peak Load Control

Perišić D., Žorić A., Obradović S., Spalević P.

Przegląd Elektrotechniczny

2012

R. 88, nr 1b

264-267

This article describes the application of the Frequency Locked Loop (FLL) in the Consumption Peak Load Control (PLC). The digital content of FLL represents the main information for optimal control. Particular significance was given to the description of the extended FLL, which is suitable for this application. Detailed solutions of FLL input module and FLL adjustments are given. The performances of the realized PLC System are demonstrated by the graphics, which are recorded on the applied PLC System.

W tym artykule opisano zastosowanie Frequency Locked Loop (FLL) do sterowania obciążeniem szczytowym Peak Load Control (PLC). Szczególne znaczenie nadano opisowi rozszerzonego FLL, który jest odpowiedni dla tej aplikacji. Podano szczegółowe rozwiązania w module FLL wejściowych i korekt FLL . PLC.