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Personal identification based on brain networks of EEG signals

Kong W., Jiang B., Fan Q., Zhu L., Wei X.

International Journal of Applied Mathematics and Computer Science

2018

Vol. 28, no. 4

745--757

Personal identification is particularly important in information security. There are numerous advantages of using electroencephalogram (EEG) signals for personal identification, such as uniqueness and anti-deceptiveness. Currently, many researchers focus on single-dataset personal identification, instead of the cross-dataset. In this paper, we propose a method for cross-dataset personal identification based on a brain network of EEG signals. First, brain functional networks are constructed from the phase synchronization values between EEG channels. Then, some attributes of the brain networks including the degree of a node, the clustering coefficient and global efficiency are computed to form a new feature vector. Lastly, we utilize linear discriminant analysis (LDA) to classify the extracted features for personal identification. The performance of the method is quantitatively evaluated on four datasets involving different cognitive tasks: (i) a four-class motor imagery task dataset in BCI Competition IV (2008), (ii) a two-class motor imagery dataset in the BNCI Horizon 2020 project, (iii) a neuromarketing dataset recorded by our laboratory, (iv) a fatigue driving dataset recorded by our laboratory. Empirical results of this paper show that the average identification accuracy of each data set was higher than 0.95 and the best one achieved was 0.99, indicating a promising application in personal identification.

Wykorzystanie zasobów FPGA do wyrównywania faz przebiegów taktujących

Matuszewski Ł., Jessa M., Ślęzak P.

Pomiary Automatyka Kontrola

2012

R. 58, nr 7

623-625

W artykule opisano projekt układu do wyrównywania fazy przebiegu o powielonej częstotliwości do fazy przebiegu, którego częstotliwość powielono. Zaproponowany algorytm wyrównywania faz można zaimplementować w układzie FPGA, w którym producent przewidział mechanizm powielania częstotliwości sygnału wejściowego. Algorytm jest bardzo oszczędny w wykorzystaniu zasobów i nie wymaga konstruowania detektorów fazy o dużej rozdzielczości pomiaru różnicy faz.

The paper describes design of a circuit that aligns the phase of a signal with multiplied frequency to the phase of a signal whose frequency is multiplying. The proposed phase aligning algorithm can be implemented in an Field Programmable Gate Array (FPGA) which supports the mechanism of frequency multiplication. The algorithm is very economical in usage of the FPGA resources and it does not require to use phase error measurements with high resolution. The principle of its work is illustrated in Figs. 1 and 2. A circuit that implements the algorithm consists of a START/STOP detector, a delay T whose value must be greater than the period of the signal with multiplied frequency, two latches and a delay line built into the FPGA whose value is controlled by a simple control module. Instead of measuring the value of the phase error between START and STOP signals, we check if signal START gets ahead of signal STOP or if it is delayed. If Qa="1" and Qb="0", the delay of the delay line from input START is increased by a quant. If Qa="1" and Qb="1" the delay of this line is decreased by a quant. In other cases the control circuit does not perform any operation. Subsequent checks are performed with frequency of signal STOP. In the design described in this paper the IODELAY line, available in Virtex-5 (XC5VLX50T), is used. The elementary delay of this line is about 75 ps. The phase alignment error observed for multiplication coefficients from 2 to 32 is between 150 ps and 240 ps.