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Performance evaluation of the multiple output queueing switch with different buffer arrangements strategy

Danilewicz G., Kabaciński W., Pleban J., Parniewicz D., Dąbrowski P.

Journal of Telecommunications and Information Technology

2006

nr 3

43-48

Performance evaluation of the multiple output queueing (MOQ) switch recently proposed by us is discussed in this paper. In the MOQ switch both the switch fabric and buffers can operate at the same speed as input and output ports. This solution does not need any speedup in the switch fabric as well as any matching algorithms between inputs and outputs. In this paper new performance measures for the proposed MOQ switch are evaluated. The simulation studies have been carried out for switches with different buffer arrangements strategy and of capacity 2×2, 4×4, 8×8, 16×16 and 32×32, and under selected traffic patterns. The simulations results are also compared with OQ switches of the same sizes.

Packet switch architecture with multiple output queueing

Danilewicz G., Głąbowski M., Kabaciński W., Kleban J.

Journal of Telecommunications and Information Technology

2004

nr 4

76-83

In this paper the new packet switch architecture with multiple output queuing (MOQ) is proposed. In this architecture the nonblocking switch fabric, which has the capacity of N _N2 N2, and output buffers arranged into N separate queues for each output, are applied. Each of N queues in one output port stores packets directed to this output only from one input. Both switch fabric and buffers can operate at the same speed as input and output ports. This solution does not need any speedup in the switch fabric as well as arbitration logic for taking decisions which packets from inputs will be transferred to outputs. Two possible switch fabric structures are considered: the centralized structure with the switch fabric located on one or several separate boards, and distributed structure with the switch fabric distributed over line cards. Buffer arrangements as separate queues with independent write pointers or as a memory bank with one pointer are also discussed. The mean cell delay and cell loss probability as performance measures for the proposed switch architecture are evaluated and compared with performance of OQ architecture and VOQ architecture. The hardware complexity of OQ, VOQ and presented MOQ are also compared. We conclude that hardware complexity of proposed switch is very similar to VOQ switch but its performance is comparable to OQ switch.