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Design optimisation of the deep trench termination for superjunction power devices

Noblecourt S., Morancho F., Isoird K., Austin P., Tasselli J.

International Journal of Microelectronics and Computer Science

2015

Vol. 6, nr 4

117--123

Among the numerous solutions developed to improve the voltage handling capability of superjunction power devices, the Deep Trench Termination (DT2) is the most adapted thanks to its lower cost and size compared to other technologies using the multiple epitaxy technique, and an easier implementation in the fabrication process. This paper presents the optimization of the Deep Trench Termination by means of TCAD 2D and 3D-simulations allowing the realization of deep trench superjunction devices (diodes and MOS transistors) for 1200 V applications. The work is focused on the influence of the dielectric passivation layer thickness and the field plate length on the breakdown voltage of a DT-SJDiode.

Analysis and optimization of LUDMOS transistors on a 0.18um SOI CMOS technology

Toulon G., Cortés I., Morancho F., Villard B.

International Journal of Microelectronics and Computer Science

2010

Vol. 1, nr 1

3-8

This paper is focused on the design and optimization of power LDMOS transistors (V br > 120 Volts) with the purpose of being integrated in a new generation of Smart Power technology based upon a 0.18 μm SOI-CMOS technology. The benefits of applying the shallow trench isolation (STI) concept along with the 3D RESURF concept in the LDMOS drift region is analyzed in terms of the main static (Ron-sp/Vbr tradeoff) and dynamic (Miller capacitance and QgxRon FOM) characteristics. The influence of some design parameters such as the polysilicon gate electrode length and the STI length are exhaustively analyzed.