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Four-channel multiplexer on surface plasmon polaritons development and research

Nevinskyі D. V., Zakalyk L. I., Lebid S. Y., Korzh H. I., Pavlysh V. A.

Challenges of Modern Technology

2016

Vol. 7, no. 1

7--11

Simulation of the surface plasmon polariton (SPP) distribution in the 10 μm long four-channel multiplexer is conducted in present paper. The excitation of the SPP was done using the 632.8 nm pulse laser with 50 fs pulse duration. The simulation processes of the SPP propagation in the fourchannel multiplexer were performed for the latter switched as a splitter as an adder. Though the obtained signal strength is low due to ohmic losses and signal reflections in the middle of the waveguide it is possible to registrate it. The detailed procedure of waveguides preparation, analysis and registration of SPP propagation is described in the paper. For the proposed model verification the two-channel 20 μm long splitter was formed by optical projection lithography. Studies have shown that the SPP is distributed throughout the whole structure of the 20 μm long two-channel splitter with a partial extinction due to ohmic losses.

Układy arytmetyki stochastycznej i ich implementacja w strukturach FPGA

Kawalec P.

Pomiary Automatyka Kontrola

2009

R. 55, nr 8

627-629

W artykule przedstawiono podstawowe układy arytmetyki stochastycznej zrealizowane w technice cyfrowej. W celu zapewnienia maksymalnej szybkości działania, syntezę układów arytmetyki stochastycznej przeprowadzono na elementach logicznych i przerzutnikach. Dla specjalizowanych układów sumatorów, subtraktorów, oraz multiplikatorów i układów potęgujących, wyznaczono dokładność przetwarzania. Przeprowadzono ich syntezę i implementację w układach FPGA, wyznaczając szybkość działania.

The paper presents fundamental circuits of stochastic arithmetic realized by means of digital technology. In order to ensure the maximum operational speed, synthesis of stochastic arithmetic circuits has been performed on logical elements and triggers. Specialized stochastic adders on NOT and NAND elements (Fig.1) as well as on multiplexers (Fig. 3) both without and with randomization of the input data (Fig. 2) have been designed for disjoint events in binary random sequences. Specification of stochastic adders has been conducted in VHDL language, and their verification - in functional simulation mode (Fig. 4). The accuracy of the stochastic adder operation has been determined, whereas synthesis and implementation of these systems in FPGA structure allowed for showing the speed of stochastic adder operation with the frequency of timing exceeding 100 MHz. Similar investigations have been carried out for specialized stochastic subtractors. For independent binary random sequences, stochastic multipliers and squaring circuits (Fig. 6) have been designed, having a structure particularly useful for realization within programmable logical FPGA structures.