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1

On k-summability of formal solutions for certain partial differential operators with polynomial coefficients

Ichinobe K., Miyake M.

Opuscula Mathematica

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2015

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Vol. 35, no. 5

625--653

EN

We study the k-summability of divergent formal solutions for the Cauchy problem of certain linear partial differential operators with coefficients which are polynomial in t. We employ the method of successive approximation in order to construct the formal solutions and to obtain the properties of analytic continuation of the solutions of convolution equations and their exponential growth estimates.

2

Numerical solution of Hammerstein integral equations in Lp spaces

Nadir M., Gagui B

Fasciculi Mathematici

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2014

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Nr 52

83--91

EN

In this work, we give conditions guarantee the boundedness of the Hammerstein integral operator in Lp spaces. The existence and the uniqueness of the solution of Hammerstein integral equation are treated under some assumptions affected to the successive approximation, so that we obtain the convergence of the approximate solution to the exact one. Finally, we treat numerical examples to confirm our results.

3

Analiza prądów upływu logarytmicznego przetwornika analogowo-cyfrowego z sukcesywną aproksymacją

Szcześniak A., Mychuda Z.

Przegląd Elektrotechniczny

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2012

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R. 88, nr 5a

247-250

PL

W artykule przedstawiono analizę logarytmicznego przetwornika analogowo-cyfrowego z sukcesywną aproksymacją (LADC) z uwzględnieniem prądów upływu. We wprowadzeniu została przedstawiona budowa oraz zasada działania LADC. W celu przeprowadzenia analizy matematycznej LADC z uwzględnieniem prądów upływu sporządzono ogólny schemat przetwornika oraz schematy zastępcze dla poszczególnych faz jego pracy. Obliczono prądy upływu dla poszczególnych faz pracy przetwornika oraz zaprezentowano bezwzględny błąd napięcia na kondensatorze akumulującym pochodzący od prądów upływu.

EN

This article is a presentation of the analysis of logarithmic analog to digital converter (LADC) taking into account leakage currents. In the introduction, LADC construction and principle of operation were described. In order to conduct mathematical analysis which takes into account leakage currents, general converter diagram and equivalent diagrams for individual phases of the converter’s work were drawn up. Leakage currents for particular work phases of the converter were calculated. Absolute error of voltage on accumulative capacitor coming from leaking currents was presented.

4

Projekt kompensacyjnego przetwornika analogowo-cyfrowego dla potrzeb wielokanałowych układów w technologii submikronowej

Otfinowski P., Zaziąbł A.

Pomiary Automatyka Kontrola

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2010

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R. 56, nr 10

1209-1212

PL

W pracy zaprezentowano projekt scalonego przetwornika analogowo-cyfrowego wykonany w technologii UMC CMOS 180nm. Przedstawiono rozwiązanie pozwalające na znaczące zmniejszenie powierzchni zajmowanej przez układ poprzez dodanie pomocniczego przetwornika C/A. Zostało przybliżone także zagadnienie odpowiedniego doboru kluczy w układach z przełączanymi pojemnościami. Ostatecznie zaprezentowany układ cechuje się szybkością konwersji wynoszącą 3 MS/s przy poborze mocy 225 žW oraz bardzo niską nieliniowością.

EN

The dynamic progress in the domain of applications involving X rays demands more sophisticated circuits for acquisition and processing of signals from the silicon detectors. This paper presents a design of an integrated analog-to-digital converter dedicated to multichannel silicon detector readout circuits. The successive approximation with charge redistribution architecture was proposed. In order to reduce the total chip area, the DAC was split into two blocks. The capacitor array used as a primary DAC and also as a sampling circuit. As a secondary DAC, the resistive voltage divider was introduced. This solution allowed reducing the total DAC area by the factor of 6, maintaining the same output voltage accuracy. The CMOS switches are described in detail, as they play important role in the switch capacitor circuits, affecting both the speed and accuracy of the primary capacitive DAC. A synchronous regenerative latch is used as a comparator. The ADC is implemented in UMC CMOS 180nm technology. The designed ADC is able to achieve conversion rates of 3 MS/s at 225 žW. The final simulation results show also low nonlinearity of the presented circuit.

5

Dynamic Programming: an overview

Sniedovich M.

Control and Cybernetics

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2006

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Vol. 35, no 3

513-533

EN

Dynamic programing is one of the major problem-solving methodologies in a number of disciplines such as operations research and computer science. It is also a very important and powerful tool of thought. But not all is well on the dynamic programming front. There is definitely lack of commercial software support and the situation in the classroom is not as good as it should be. In this paper we take a bird's view of dynamic programming so as to identify ways to make it more accessible to students, academics and practitioners alike.

6

Dijkstra's algorithm revisited: the dynamic programming connexion

Sniedovich M.

Control and Cybernetics

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2006

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Vol. 35, no 3

599-620

EN

Dijkstra's Algorithm is one of the most popular algorithms in computer science. It is also popular in operations research. It is generally viewed and presented as a greedy algorithm. In this paper we attempt to change this perception by providing a dynamic programming perspective on the algorithm. In particular, we are reminded that this famous algorithm is strongly inspired by Bellman's Principle of Optimality and that both conceptually and technically it constitutes a dynamic programming successive approximation procedure par excellence. One of the immediate implications of this perspective is that this popular algorithm can be incorporated in the dynamic programming syllabus and in turn dynamic programming should be (at least) alluded to in a proper exposition/teaching of the algorithm.