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1

Improving LUT count of FPGA-based sequential blocks

Barkalov Alexander, Titarenko Larysa, Mazurkiewicz Małgorzata, Krzywicki Kazimierz

Bulletin of the Polish Academy of Sciences. Technical Sciences

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2021

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Vol. 69, nr 2

art. no. e136728

EN

Very often, a digital system includes sequential blocks which can be represented using a model of the finite state machine (FSM). It is very important to improve such FSM characteristics as the number of used logic elements, operating frequency and consumed energy. The paper proposes a novel technology-dependant design method targeting LUT-based Mealy FSMs. It belongs to the group of structural decomposition methods. The method is based on encoding the product terms of Boolean functions representing the FSM circuit. To diminish the number of LUTs, a partition of the set of internal states is constructed. It leads to three-level logic circuits of Mealy FSMs. Each function from the first level requires only a single LUT to be implemented. The method of constructing the partition with the minimum amount of classes is proposed. There is given an example of FSM synthesis with the proposed method. The experiments with standard benchmarks were conducted. They show that the proposed method can improve such FSM characteristics as the number of used LUTs. This improvement is accompanied by a decrease in performance. A positive side effect of the proposed method is a reduction in power consumption compared with FSMs obtained with other design methods.

2

Improving characteristics of LUT-based Mealy FSMs

Barkalov Alexander, Titarenko Larysa, Mielcarek Kamil

International Journal of Applied Mathematics and Computer Science

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2020

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Vol. 30, no. 4

745--759

EN

Practically, any digital system includes sequential blocks represented using a model of finite state machine (FSM). It is very important to improve such FSM characteristics as the number of logic elements used, operating frequency and consumed energy. The paper proposes a novel technology-dependent design method targeting a decrease in the number of look-up table (LUT) elements and their levels in logic circuits of FPGA-based Mealy FSMs. It produces FSM circuits having three levels of logic blocks. Also, it produces circuits with regular systems of interconnections between the levels of logic. The method is based on dividing the set of internal states into two subsets. Each subset corresponds to a unique part of an FSM circuit. Only a single LUT is required for implementing each function generated by the first part of the circuit. The second part is represented by a multi-level circuit. The proposed method belongs to the group of two-fold state assignment methods. Each internal state is encoded as an element of the set of states and as an element of some of its subsets. A binary state assignment is used for states corresponding to the first part of the FSM circuit. The one-hot assignment is used for states corresponding to the second part. An example of FSM synthesis with the proposed method is shown. The experiments with standard benchmarks are conducted to analyze the efficiency of the proposed method. The results of experiments show that the proposed approach leads to diminishing the number of LUTs in the circuits of rather complex Mealy FSMs having more than 15 internal states. The positive property of this method is a reduction in energy consumption (without any overhead cost) and an increase in operating frequency compared with other investigated methods.

3

Quality testing model for unit prototype technological devices

Dobrodziej J., Mazurkiewicz A., Zbrowski A.

Scientific Problems of Machines Operation and Maintenance

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2011

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Vol. 46, nr 1

29-44

EN

The article presents the model of testing individually manufactured unique prototype technical devices. Furthermore, problems occurring in such prototype testing are identified, and, on the basis, the assumptions of the model for quality tests of prototype technical solutions are made. Essential components of the model, including structural and process decomposition procedures, are discussed. Moreover, potential applications of the model are analysed and indicated. Results of the model verification are presented using the example of selected, technologically advanced prototype devices.

PL

W artykule przedstawiono model badania prototypowych urządzeń technicznych wytwarzanych jednostkowo. Zidentyfikowano praktyczne problemy występujące w badaniach takich prototypów. Na tej podstawie sformułowano założenia do budowy modelu badań jakości rozwiązań prototypowych. Zaprezentowano kluczowe komponenty modelu, w tym procedury dekompozycji strukturalnej i procesowej. Przeanalizowano możliwości zastosowań modelu. Weryfikację modelu przedstawiono na wybranych, zaawansowanych technicznie prototypowych jednostkowych urządzeniach technicznych.

4

Structural decomposition of transfer matrix of positive normal hybrid systems

Kaczorek T.

Archives of Control Sciences

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2008

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Vol. 18, no. 4

399-413

EN

A new class of positive normal hybrid linear systems is introduced. It is shown that: 1) the inverse matrix of the characteristic system matrix is normal if and only if its greatest common divisor of (n - 1)-th order minors is equal to one, 2) the rational matrix is normal if and only if its McMillan polynomial is equal to the last common denominator, 3) the rational matrix has the structural decomposition of its transfer matrix if and only if the transfer matrix is normal. A procedure for computation of the structural decomposition of a normal transfer matrix is proposed. The considerations are illustrated by numerical examples.