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Analog circuits specification driven testing by the means of digital stream and non-linear estimation model optimized evolutionarily

Golonek T., Chruszczyk Ł.

Bulletin of the Polish Academy of Sciences. Technical Sciences

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2020

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Vol. 68, nr 6

1283--1299

EN

The method described in this work allows to determine the optimal distribution of pulses of digital signal as well as the non-linear mathematical model based on a multiple regression statistical analysis, which are specialized to an effective and low-cost testing of functional parameters in analog electronic circuits. The aim of this concept is to simplify the process of analog circuit specification validation and minimize hardware implementation, time and memory requirements during the testing stage. This strategy requires simulations of the analyzed analog electronic circuit; however, this effort is done only once – before the testing stage. Then, validation of circuit specification can be obtained after a quick, very low-cost procedure without time consuming computations and without expensive external measuring equipment usage. The analyzed test signature is a time response of the analog circuit to the stream of digital pulses for which distributions were determined during evolutionary optimization cycles. Besides, evolutionary computations assure determination of the optimal form and size of the non-linear mathematical formula used to estimate specific functional parameters. Generally, the obtained mathematical model has a structure similar to the polynomial one with terms calculated by means of multiple regression procedure. However, a higher ordered polynomial usage makes it possible to reach non-linear estimation model that improves accuracy of circuit parametric identification. It should be noted that all the evolutionary calculations are made only at the before test stage and the main computational effort, for the analog circuit specification test design, is necessary only once. Such diagnosing system is fully synchronized by a global digital signal clock that precisely determines time points of the slopes of input excitation pulses as well as acquired output signature samples. Efficiency of the proposed technique is confirmed by results obtained for examples based on analog circuits used in previous (and other) publications as test benchmarks.

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Application of Neural Network for Testing Selected Specification Parameters of Voltage-Controlled Oscillator

Grzechca D., Temich S.

International Journal of Electronics and Telecommunications

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2018

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Vol. 64, No. 2

203--207

EN

In this paper, the application of the Artificial Neural Network (ANN) algorithm has been used for testing selected specification parameters of voltage-controlled oscillator. Today, mixed electronic circuits specification time is an issue. An analog part of Phase Locked Loop is a voltage-controlled oscillator, which is very sensitive to variation of the technology process. Fault model for the integrated circuit voltage control oscillator (VCO) in ring topology is introduced and the before test stage classificatory is designed. In order to reduce testing time and keep the specification accuracy (approximation) on the high level, an artificial neural network has been applied. The features selection process and output coding for specification parameters are described. A number of different ANN have been designed and then compared with real specification of the VCO. The results obtained gives response in short time with high enough accuracy.

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An analogue electronic circuits specification driven testing with the use of time domain response's features

Jantos P., Golonek T., Rutkowski J.

Elektronika : konstrukcje, technologie, zastosowania

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2011

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Vol. 52, nr 12

65-68

EN

This paper presents a deterministic method of analogue electronic circuits' specification driven testing. This method is based on an analysis of a circuit-under-test time-domain response's to a pulse excitation. We are extracting the response's and its first order derivative minima and maxima locations. Then, the tested circuit's specifications are mapped into response's features planes. At the test stage, extracted reaponse's features are used to predict specifications values. The decision about the test result (GO/NO-GO) is made with a simple deterministic inference system. Our testing method has been verified with a use of an exemplary circuit, a low-pass filter.

PL

W artykule przedstawiono deterministyczną metodę testowania analogowych układów elektronicznych. Metoda ta bazuje na wykorzystaniu cech odpowiedzi testowanego układu na wymuszenie w dziedzinie czasu. W zapisie odpowiedzi znajdowane są kolejne ekstrema. Specyfikacje układu testowanego są aproksymowane w przestrzenie zdefiniowanej czasem wystąpienia oraz wartością kolejnych cech odpowiedzi. Prosty, deterministyczny system ekspercki pozwala na stwierdzenie, czy testowany układ spełnia założenia specyfikacji. Prezentowana metoda testowania została zweryfikowana z wykorzystaniem przykładu obliczeniowego - filtru dolnoprzepustowego.