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Automated software-based in-field self-test program synthesis

Jasnetski A., Ubar R., Tsertov A

International Journal of Microelectronics and Computer Science

2017

Vol. 8, nr 2

57--64

This paper presents a methodology to automate functional Software-Based Self-Test program development. We rely on the previously published research on modeling processors using subclass of acyclic directed graphs called High-Level Decision Diagrams (HLDD). The HLDD model of the processor gets generated from its Instruction Set Architecture. The HLDD model is then used together with beforehand prepared assembly program templates in the generation of the complete self-test program. The research presented in this paper includes examples of test generation for the 32-bit SPARCv8 microprocessor Leon 3. The experimental results demonstrate that automatically generated SBST program obtains comparable to the state-of the art fault coverage data.

Dynamic Ruleset Based Online Concurrent Testing of Functional Faults for Embedded Controllers

Daniel P., Chandel R.

Przegląd Elektrotechniczny

2014

R. 90, nr 1

111--114

Concurrent fault testing is mandatory in critical embedded systems like automobile applications. Architectures of concurrent testing are proposed in the present work, where testing is non-intrusive. The concept that embedded program has several tasks is exploited here. The hardware overhead of the test architecture implemented on the controller of OC8051 is minimal. It is easily scalable. Error detection latency is kept at a few cycles and cumulative functional error coverage is 100%. The architectures are compared with the best of the existing methods.

Współbieżne testowanie jest często obowiązkowe w systemach wbudowanych. W artykule zaprezentowano architektury tego typu systemów gdzie wbudowany program wykonuje wiele zadań. Analizowano opóźnienie w wykrywaniu błędów oraz uwarunkowania sprzętowe.