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EN
Although increasing the number of switches increases the switch losses, most designed controllers focus on controlling an inverter circuit with more than six switches. The paper aims to address this issue that arises in implementation of the voltage source inverter (VSI) for brushless DC (BLDC) motors. It optimises the sinusoidal pulse width modulation (PWM) controller, minimising total harmonic distortion (THD) while keeping the VSI’s circuit at six switches to avoid increased switching losses. This was achieved by applying an artificial neural network (ANN) to generate a signal, which combines with the already existing reference and carrier signals. The addition of the new signal to the existing signals contributed to generating more pulses compared with the conventional sinusoidal PWM. Simulink was used to design the system and analyse its performance with the conventional and neutral point clamped (NPC) VSI systems. Results indicated that the proposed system performs better when controlled with an LCC filter. Compared with the control experiments, its output waveform has the lowest THD value, which is 6.04%. The switching losses of all the systems were also computed. Results from the computation indicated that the proposed system is capable of reducing the switching losses by 0.6 kW compared with the NPC VSI brushless DC motor (BLDCM) system. BLDCM speed was tested across various conditions; the results are reported in Section 5.
EN
Due to recent developments in the field of high-power and medium-voltage, the multilevel inverter has raised to such an extent owing to some of its amazing facts regarding harmonic spectrum, ease in control, reduced electromagnetic interference (EMI), filterless circuit, stress on power switches, common-mode voltage. This paper well describes a novel architecture of a single-phase multilevel inverter using a lesser number of overall components, especially the power switches. The proposed topology is generalized in the structure that can generate any number of voltage steps. A 7-level structure of the proposed topology is explained and is elaborately discussed. Simulation is carried out in MATLAB and corresponding experimental results verify the existence of the proposed multilevel inverter. The real-time experimental results were presented and are well verified by the simulation results for 7-level as well for 13-level across RL-Load. The nature of load current is also indicated as per the nature of load voltage. Nevertheless, the topology is further compared with some of the recent literature and found superior in each respect.
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