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An improved effective index method for planar multimode waveguide design on an silicon-on-insulator (SOI) platform

Le T T

Optica Applicata

2013

Vol. 43, nr 2

s. 271--277

In this paper, an improved effective index method (EIM) for designing planar multimode waveguides on the silicon-on-insulator (SOI) platform is presented. The proposed method predicts the evolution of the fields more accurately than the conventional effective index method. This improved method is particularly suited to the design of multimode interference (MMI) couplers.

Optical switch based on cascaded SOI nonlinear directional coupler

Tao Q., Luo F., Cai D., Liang Q., Wan Z., Song X., Liu X.

Optica Applicata

2011

Vol. 41, nr 3

669--678

In this paper, we calculate three effective refractive indexes for cascaded silicon-on-insulator (SOI) nonlinear directional coupler. For each effective refractive index, the coupling length LC, core-to-distance-ratio K and switching threshold power Pi, m are calculated, respectively. However, there are some fabrication errors, which are ?W, ?H, ?K in the height of Si layer and width of Si layer and error of core-to-distance-ratio. We have analyzed the influence of power transmission efficiency Ti, j and relative transmission efficiency error ?i, j caused by the change of ?W, ?H, ?K. Furthermore, we find the tolerance range of ?W, ?H, ?K for Ti, j and ?i, j in couplers a, b, c. The other four input pulses with different powers are switched to four different ports. Although output pulses show some little compression and loss, the value of ? is very small and output pulse waveforms are not affected seriously. The basic switching function has been realized, so this design is proved to be effective.

On-wafer wideband characterization: a powerful tool for improving the IC technologies

Lederer D., Raskin J. P.

Journal of Telecommunications and Information Technology

2007

nr 2

69-77

In the present paper, the interest of wideband characterization for the development of integrated technologies is highlighted through several advanced devices, such as 120 nm partially depleted (PD) silicon-on-insulator (SOI) MOSFETs, 120 nm dynamic threshold (DT) voltage - SOI MOSFETs, 50 nm FinFETs as well as long-channel planar double gate (DG) MOSFETs.

Challenges for 10 nm MOSFET process integration

Östling M., Malm B. G., Haartman M., Hallstedt J., Zhang Z., Hellström P. E., Zhang S.

Journal of Telecommunications and Information Technology

2007

nr 2

25-32

An overview of critical integration issues for future generation MOSFETs towards 10 nm gate length is presented. Novel materials and innovative structures are discussed. The need for high-k gate dielectrics and a metal gate electrode is discussed. Different techniques for strain-enhanced mobility are discussed. As an example, ultra thin body SOI devices with high mobility SiGe channels are demonstrated.