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1

An active power filter based on a hybrid converter topology – Part 1

Gwóźdź Michał, Ciepliński Łukasz

Bulletin of the Polish Academy of Sciences. Technical Sciences

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2021

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Vol. 69, nr 1

art. no. e136218

EN

This paper presents a concept of a shunt active power filter, which is able to provide more precise mapping of its input current drawn from a power line in a reference signal, as compared to a typical filter solution. It can be achieved by means of an interconnection of two separate power electronics converters making, as a whole, a controlled current source, which mainly determines the quality of the shunt active filter operation. One of these power devices, the “auxiliary converter”, corrects the total output current, being a sum of output currents of both converters, toward the reference signal. The rated output power of the auxiliary converter is much lower than the output power of the main one, while its frequency response is extended. Thanks to both these properties and the operation of the auxiliary converter in a continuous mode, pulse modulation components in the filter input current are minimized. Benefits of the filter are paid for by a relatively small increase in the complexity and cost of the system. The proposed solution can be especially attractive for devices with higher output power, where, due to dynamic power loss in power switches, a pulse modulation carrier frequency must be lowered, leading to the limitation of the “frequency response” of the converter. The concept of such a system was called the “hybrid converter topology”. In the first part of the paper, the rules of operation of the active filter based on this topology are presented. Also, the results of comparative studies of filter simulation models based on both typical, i.e. single converter, and hybrid converter topologies, are discussed.

2

Switched Current Sigma-Delta Modulator with a New Comparator Structure Designed Based on VHDL-AMS Description

Śniatała P, Handkiewicz A, Naumowicz M., Szczęsny S., Melosik M., Katarzyński P., Kropidłowski M.

International Journal of Electronics and Telecommunications

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2013

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Vol. 59, No. 4

391-396

EN

The paper presents a VHDL-AMS based approach to the Switched-Current (SI) Sigma-Delta Modulator design. The prototype VHDL-AMS description, with the help of elaborated EDA tools, is automatically translated into the SI realization. Another tool helps the designer to create the layout. The paper also describes a new current mode comparator, which is used in the design. Postlayout simulation results are presented.

3

Monolityczne układy konwerterów sigma-delta do pomiaru wartości skutecznej napięcia i ich porównanie ze scalonymi konwerterami klasycznymi

Korytkowski J.

Pomiary Automatyka Robotyka

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2012

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R. 16, nr 7-8

84-89

PL

W pracy omówiono zasadę działania współczesnych monolitycznych układów konwerterów sigma-delta stosowanych do formowania analogowego sygnału pomiarowego o wartości skutecznej napięcia. Dokonano przeglądu właściwości monolitycznych układów konwerterów sigma-delta do pomiaru wartości skutecznej napięcia i porównano z właściwościami monolitycznych klasycznych konwerterów stosowanych do takich pomiarów. Istotnymi zaletami monolitycznych układów konwerterów sigma-delta do pomiaru wartości skutecznej są: duża dokładność formowania analogowego wyjściowego sygnału pomiarowego, bardzo mały pobór mocy na wejściu oraz szerokie pasmo częstotliwościowe mierzonego napięcia wejściowego.

EN

The monolithic sigma-delta converters are very useful for measurement root-mean-square time-varying voltage circuits. The fig. 1 shows converter block diagram, which got possibility to describe the mathematical function for calculation RMS value of input AC voltage. The fig. 2 shows block diagram of multiplier-divider circuit containing identical two controlled elements having the very same controlled amplification. In the fig. 3 is shown the circuit diagram of sigma-delta modulator and characteristic of comparator, which is a part of the modulator. According to fig. 3 was formulated equation (15) as the characteristic description of multiplier-divider circuits, which is the main element of sigma-delta true RMS converter for input voltage measurement. The part 3 of this paper describes the parameters review of monolithic RMS converters. The table 1 presents the parameter values of selected group RMS converters, which are delivered by several much known firms. The converters parameters analysis shows, that monolithic sigma-delta converters have very good qualities in the parameter field of accuracy, minimal signal power consumption and wide frequency band of input measurement signals.

4

Built-in test scheme for detection, classification and evaluation of nonlinearities

Toczek W., Kowalewski M.

Metrology and Measurement Systems

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2009

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Vol. 16, nr 1

47-59

EN

This paper presents a Built-In Test (BIT) scheme intended for detection of nonlinearities, classification of the form of nonlinearity and evaluation of the total harmonic distortion (THD) of the signal under test, without using expensive automatic test equipment (ATE). The tester is based on a sigma-delta modulator located on a board and artificial neural networks implemented in an attached personal computer. The proposition is verified by simulation in a Matlab/Simulink environment for three classes of nonlinearities - clipping effect, crossover distortion and rate limiting. The model of the Van der Pol oscillator is used as a programmable reference source of nonlinear oscillation.

5

An FPGA-based sigma-delta audio DAC

Kulka Z., Lewandowski M.

Elektronika : konstrukcje, technologie, zastosowania

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2009

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Vol. 50, nr 4

107-111

EN

This paper presents the sigma-delta audio digital-to-analog converter (DAC) implemented on a single field programmable gate array (FPGA) for non-commercial application. The simulation results and FPGA-based hardware implementation are shown.

PL

W pracy przedstawiono implementację fonicznego przetwornika cyfrowo-analogowego (c/a) sigma-delta w programowalnej strukturze logicznej FPGA do zastosowania niekomercyjnego. Podano wyniki symulacji oraz wyniki działania przetwornika zaimplementowanego we wspomnianej strukturze FPGA.

6

Sigma-delta modulator for force measurement based on the use of a flip-flop circuit and presentation of simulated results

Kollar M.

Metrology and Measurement Systems

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2004

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Vol. 11, nr 1

3-19

EN

This paper describes a flip-flop circuit-based sigma-delta modulator for force measurement. The main part of the proposed system is a modified flip-flop used as a comparator, inside of which switched capacitors replace the classical load resistors. The functional principle lies in the fact that if capacitive asymmetry caused by the force to be measured, is such that the flip-flop holds a stable state where, for example, a higher voltage is on a second transistor, then it produces a higher force between the parallel plates connected to the same transistor to decrease the resulting capacitive asymmetry. The main advantage of the flip-flop, besides its simplicity, is the compensation of the influence of flicker noise, which is mathematically described in this paper. The theoretical conclusions are compared with the results of simulations with TSPICE and Matlab-Simulink, with respect to the measurement system realized in 0.8 [mi]m CMOS technology. The results were in agreement with theoretical results.

PL

Artykuł przedstawia modulator typu sigma-delta do pomiaru siły. Główną jego częścią jest zmodyfikowany układ komparatora oparty na przerzutnikach, w którym pojemności przełączane zastępują klasyczne rezystory. Zasada działania opiera się na zjawisku zakłócenia asymetrii pojemności mierzoną siłą. Główną zaletą użycia przerzutników w tym układzie, poza ich prostotą, jest kompensacja wpływu szumów typu flicker, co udowodniono w pracy. Wnioski teoretyczne są zgodne z wynikami symulacji dokonanych w TSPICE i pakiecie Matlab-Simulink. Układ opracowano w technologii CMOS 0.8 mikrometra.

7

Oversampling sigma-delta analog-to-digital converters modeling based on VHDL

Baraniecki R., Dąbrowski P., Hejn K.

Prace Przemysłowego Instytutu Elektroniki

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1998

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nr 132

163-171

EN

The paper presents a VHDL model of an oversampling sigma-delta analog-to-digital converter created on the behavioral hierarchy level. Although VHDL has been primarily devoted to digital circuit design, it can also be applied to certain mixed-signal circuits. The model of the analog part is as simple as possible and includes only necessary parameters that enable to determine the potential resolution of a converter. The model of the digital parttis described in the synthesizable subset of VHDL and parameterized according to the word length and the type of arithmetic applied. The validation process of the converter model is also shown. It is performed by a VHDL simulator and a postprocessor tool enabling to carry out FFT. Simulation results enclosed prove the efficiency of the design approach presented.

8

Measurement and enhancement of multistage sigma-delta modulators

Hejn K., Murphy P., Kale I.

Prace Przemysłowego Instytutu Elektroniki

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1998

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nr 132

18-24

EN

Over-sampled sigma-delta modulators are at present the only solution to realizing high resolution (>16 bits) A/D converters. They are relacively robust against circuit imperfections and well suited for VLSI implementation. Their theoretical basis is well founded in many excellent papers. However, it has to be pointed out that those analyses have not considered effects such as gain mismatch of the stages, timing. Ditters, input noise. Instability of thresholders the asymmetry in the rise fall times of the pulses generated etc. Knowing sigma-delfa modulators theory is not the same as knowing what to do when asked to measure a signal spectrum with 1 dB resolution or -130 dB harmonic distortion. These numerical values are typical for sigma-delta structures with 20-bit potential. This paper specifically addresses such problems suggests some solutions. Simulations known that the key factors are: a coherent measurement event (explicit) digitizing and polyphase recursive all-pass filtering.

9

Fixedpoint arihmetic effects in all-pass filters of oversampling sigma-delta (analog to digital) converters

Dąbrowski P., Baraniecki R., Hejn K., Rosiński A.

Prace Przemysłowego Instytutu Elektroniki

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1998

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nr 132

113-118

EN

Oscillations arising from two's complement arithmetic rounding applied in all-pass filters are described. The all-pass filters in two-path phase shifter structure build a digital filter of oversampling sigma-delta converter - decimator. The paper also shows that during a top-down design process of the all-pass filters such oscillations can easily be suppressed.

10

An HDL-A/VHDL model of an oversampling sigma-delta analog to digital converter

Baraniecki R., Dąbrowski P., Hejn K.

Prace Przemysłowego Instytutu Elektroniki

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1998

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nr 132

120-127

EN

The paper presents a mixed HDL-A/VHDL model of an oversampling sigma-delta analog-to-digital converter created on the behavioural hierarchy level. The model of the analog part is coded in HDL-A and includes only necessary parameters that enable to determine the potential resolution of the converter. The model of the digital part is described in the synthesizable subset of VHDL and parameterized according to the word length and the type of arithmetic applied. Simulation results enclosed prove the efficiency of the design approach presented.

11

A VHDL model of an oversampling sigma-delta analogto digital converter

Dąbrowski P., Baraniecki R., Hejn K., Rosiński A.

Prace Przemysłowego Instytutu Elektroniki

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1998

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nr 132

87-92

EN

The IEEE Std. 1076 of VHDL has been primarily devoted to digital circuits' design. However, it can also be applied to certain mixed-signal circuits. An oversampling sigma-delta analog to digital converter has been chosen as a suitable example for behavioral modeling and simulation. The efficiency of the approach is analyzed in the SIGNAL PROCESSING WORKSYSTEM and VANTAGE Spreadsheet environments.

12

A decimation filter design from VHDL specification

Baraniecki R., Dąbrowski P., Hejn K.

Prace Przemysłowego Instytutu Elektroniki

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1998

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nr 132

156-161

EN

The paper presents a design of a decimation filter - decimator, which can be used as a digital part of an oversampling sigma-delta analog-to-digital converter. The decimator model has been developed in VHDL as a macro parameterized with respect to the word length. A special architecture based on an arithmetic unit aod a sequencer has been chosen to minimize the circuit area. Such an approach was possible due to the regular structure of the decimator.