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1

Enhanced clock gating technique for power optimization in SRAM and sequential circuit

Ashok Kumar C., Madhavi B.K., Lal Kishore K.

Journal of Automation Mobile Robotics and Intelligent Systems

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2021

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Vol. 15, No. 2

32--38

EN

Low power VLSI designs are having wide variety of application usage in real-time. VLSI circuits are analyzed with various power reduction strategies. Existing approaches are used the clock frequency control, switching activity and scaling factor for power reduction. The glitching problem and clock triggering issues are higher therefore; the proposed work utilized the improved circuit of clock gating technique. In this proposed work, the enhanced clock gating with D-latch model is constructed to obtain the less power consumption. The traditional clock gating technique is improved by adding clock triggering on LATCH circuit and adding buffer circuit between the source and load circuitry to reduce the clock switching issues like gitching and clocking activity. Here the SRAM and sequential counter circuits are designed to utilize the power reduction strategy for improving the performance. This is applicable for various applications in real world and utilizing the FPGA and DSP application specific circuits. Experimental results are analyzed to obtain the power reduction result of SRAM and sequential circuit. Area, power, and delay are obtained the better results as compared with the previous work. Overall, design is performed using Xilinx 14.2 ISE suit.

2

The Implementation of the Parallel Scrambler Scheme for the IEEE 802.11 Standard

Kudinov A., Antimirov Y., Tyshchenko I., Popova M., Cherepanov A.

International Journal of Electronics and Telecommunications

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2018

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Vol. 64, No. 1

91--94

EN

This article is devoted to the development of the scrambler circuit. Nowadays, new WiFi standard IEEE 802.11 is being put into operation, so that there is a huge need in modern, energy-efficient algorithms, which will be used in the data transmission. Consequently, some of the scrambler circuits, which could be implemented for the IEEE 802.11 standard are described with its comparison. In addition, an example in Python is given for readers to use it in their researches.

3

Dekompozycja sieci działań układów sekwencyjnych w celu obniżenia poboru mocy

Bułatowa I., Salauyou V., Matujewicz P.

Pomiary Automatyka Kontrola

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2014

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R. 60, nr 7

501--503

PL

Opracowana została metoda syntezy układów sekwencyjnych o obniżonym poborze mocy, algorytmy sterowania których opisywane są za pomocą sieci działań. Metoda syntezy polega na dekompozycji sieci działań na fragmenty realizowane w postaci oddzielnych automatów połączonych w dwupoziomową strukturę hierarchiczną. Zmniejszenie poboru mocy osiąga się przez odłączenie sygnału synchronizacji od nieaktywnych w danym momencie automatów. Zaproponowano schemat bramkowania sygnału synchronizacji z wykorzystaniem sygnałów struktury hierarchicznej. Opracowany został algorytm dekompozycji sieci działań na fragmenty realizowane jako komponenty struktury hierarchicznej. Przeprowadzone badania potwierdziły efektywność zaproponowanej metody.

EN

In this paper a method for low-power design of hierarchical structures of sequential circuits specified by the Algorithmic State Machine (ASM) charts is presented. The proposed method uses a decomposition of the original sequential circuit into the smaller automata which are connected in a two-level hierarchical structure topology (Fig.1). A clock-gating approach [4, 5] is used to reduce power consumption of the sequential circuit. Due to this approach the power can be saved by clocking only one automaton of hierarchical structure at a time while the clock to the other automata is gated. As a result, only one automaton of hierarchical structure is active at any time while the others are idle, thus reducing the switching activity and minimizing the power dissipation. The algorithm of decomposition of the ASM chart into the fragments, which are implemented as components of a hierarchical structure, has been developed. The clockgating circuit (Fig. 2) which uses the control signals generated by the hierarchical structure is proposed. The power simulation method used to estimate the power consumption for original and decomposed circuits is described. Experimental results show that the proposed partitioning technique can reduce power consumption, on average 20.31%, over the original undecomposed circuit. An additional power saving is available by using special state encoding which reduces the switching activity of sequential circuits.

4

Zastosowanie metody syntezy wielopoziomowych układów kombinacyjnych do realizacji części kombinacyjnej wspólnego modelu automatów skończonych Mealy’ego i Moore’a

Klimowicz A.

Przegląd Elektrotechniczny

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2013

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R. 89, nr 11

105-108

PL

Praca dotyczy problemu syntezy układu sekwencyjnego w oparciu o programowalne układy logiczne. Cechą szczególną zastosowanej metody jest wykorzystanie wartości zmiennych wyjściowych jako kodu lub części kodu stanów wewnętrznych automatu skończonego. Do uproszczenia funkcji wyjść i funkcji wzbudzeń elementów pamięci automatu zastosowano metodę syntezy wielopoziomowych układów kombinacyjnych wykorzystującą sprzężenia zwrotne układu programowalnego. Praca zawiera także wyniki badań eksperymentalnych metody.

EN

In this paper, a problem of synthesis of sequential circuit on programmable logic device was presented. A special feature of the method is application of values of output variables as a code or as a part of code of internal states of a finite automata. The synthesis method of multilevel combinational circuits, which uses feedbacks of PLD macrocells to synthesis of finite state machines was applied to simplification of combinational part of state machine. The experimental results of synthesis of the improved method are presented in the paper.

5

Synthesis of finite state machines for implementation with programmable structures

Łuba T., Borowik G., Kraśniewski A.

Electronics and Telecommunications Quarterly

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2009

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Vol. 55, No 2

183-200

EN

Sensible application of programmable structures to the realization of digital systems cannot take place without computer aided design systems. It is particularly important when the design is intended for novel programmable structures containing LUT-based cells and embedded memory blocks, since traditional methods for technology mapping are oriented towards gate structures and based on minimization and factorization of Boolean functions. This article focuses on finite state machine synthesis including logic optimization techniques, the technology mapping techniques, and the techniques that provide the resulting circuits with concurrent error detection capability. It is shown that a considerably more effective method of synthesis intended for CPLD and FPGA structures is based on the decomposition scheme.

6

Improved state encoding for FSM implementation in FPGA structures with embedded memory blocks

Borowik G.

Electronics and Telecommunications Quarterly

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2008

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Vol. 54, No 1

9-28

EN

Modern FPLD devices have a very complex structure. They combine PLA-like structures as well as FPGA's and even memory-based structures. However, the lack of an appropriate synthesis method does not allow the features of the modern FPLD's to be fully exploited. In this paper, an important problem of state assignment for an FSM as an extension of the previous research on ROM-based FSM implementation is presented. We pinpoint the sources of additional optimization of the functional decomposition and relate them to the state encoding conditions. The method is based on a reduction of a state assignment problem to a graph coloring problem. To this end, the so called multi-graph of incompatibility of memory T-words is applied. As a result, a new design technique for implementation of sequential circuits using embedded memory blocks of FPGA's has been developed. Preliminary experimental results- are extremely encouraging.

7

Synteza układów sekwencyjnych w strukturach FPGA z wbudowanymi blokami pamięci

Łach J., Sapiecha E., Zbierzchowski B.

Przegląd Telekomunikacyjny + Wiadomości Telekomunikacyjne

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2003

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nr 2-3

81-86

PL

Przedstawiono ogólną metodę syntezy układów sekwencyjnych w strukturach z wbudowanymi pamięciami. Metoda wykorzystuje pojęcie dekompozycji szeregowej i polega na dekompozycji bloku pamięci na dwa bloki: układ modyfikacji adresu i pamięć o zredukowanej pojemności. Umożliwia ona implementację układów typu FSM przekraczających wymagane pojemności pamięci w dostępnych modułach FPGA. Wyniki badań eksperymentalnych pokazują, że efektywność metody jest znacznie większa niż w komercyjnych narzędziach projektowania.

EN

A general method for the synthesis of sequential circuits using embedded memory blocks is presented. The method is based on the serial decomposition concept and relies on the decomposition of memory block into two blocks: a combinational address modifier and a smaller memory block. This makes possible to implement FSM that exceed available memory through using embedded memory blocks and additional programmable logic. The experimental data demonstrate the efficiency of the proposed approach and large improvements over results obtained by commercially available tools.

8

Design of Digital Circuits with Current-mode Gates

Guziński A., Pawłowski P., Czwyrow D., Kaniewski J., Maslennikow O., Maslennikowa N., Rataj D.

Bulletin of the Polish Academy of Sciences. Technical Sciences

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2000

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Vol. 48, nr 1

73-91

EN

The paper deals with the problem of digital circuit design based on the current-mode gates - novel digital elements operating with a constant, continuous power supply current. The purpose is the provision of a high level noise immunity of chips which contain both analog and digital circuits. The logical properties and several identities of the current-mode logic and some expressions for a conversion of the Boolean functions into the current-mode functions are represented. Based on these properties and expressions, the approaches of minimizing the current logic functions are derived. Moreover, a new concept of the low-voltage current-mode gates realization and the two new types of the current-mode gates are designed for the next reduction of the current mode digital circuit complexity. Based on these approaches and new types of the gates, the functional schemes of some current-mode combinatorial and sequential circuits are derived. The obtained circuits are characterized by lower hardware overheads (up to 35%) in comparison with similar hardware based on the classical voltage type gates.