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Zero-Suppression Trigger Mode for GEM Detector Measurement System

Kolasinski Piotr, Pozniak Krzysztof, Wojenski Andrzej, Linczuk Pawel, Krawczyk Rafal, Gaska Michal, Zabolotny Wojciech, Kasprowicz Grzegorz, Chernyshova Maryna, Czarski Tomasz

International Journal of Electronics and Telecommunications

2021

Vol. 67, No. 1

103--108

A novel approach to a trigger mode in the Gas Electron Multiplier (GEM) detector readout system is presented. The system is already installed at WEST tokamak. The article briefly describes the architecture of the GEM detector and the measurement system. Currently the system can work in two trigger modes: Global Trigger and Local Trigger. All trigger processing blocks are parts of the Charge Signal Sequencer module which is responsible for transferring data to the PC. Therefore, the article presents structure of the Sequencer with details about basic blocks, theirs functionality and output data configuration. The Sequencer with the trigger algorithms is implemented in an FPGA chip from Xilinx. Global Trigger, which is a default mode for the system, is not efficient and has limitations due to storing much data without any information. Local trigger which is under tests, removes data redundancy and is constructed to send only valid data, but the rest of the software, especially on the PC side, is still under development. Therefore authors propose the trigger mode which combines functionality of two existing modes. The proposed trigger, called Zero Suppression Trigger, is compatible with the existing interfaces of the PC software, but is also capable to verify and filter incoming signals and transfer only recognized events. The results of the implementation and simulation are presented.

Application of Concurrency in the Asynchronous Design of Write-after-read Operations

Toosizade N., Zaky S.G.

Fundamenta Informaticae

2009

Vol. 95, nr 1

31-52

This paper introduces enhancements to the synthesis of circuits that involve write-afterread (WAR) operations and use the four-phase handshake protocol. The paper demonstrates that the use of edge-triggering makes possible many useful trade-offs among speed, area and powerdelay product. Significant increases in speed are possible as a result of increased concurrency in the circuit's operation, which compensates for much of the penalty associated with the down phase of the four-phase protocol. It is also shown that concurrency can be increased by the judicious insertion of T-elements in the system's control structure. Simulation results for a 16-bit accumulator showed a speed increase of 50% and a reduction of 23% in the power-delay product. The speed of a radix-4 Booth multiplier increased by over 27% and its area and energy consumption were reduced by 5%. These results were derived using test circuits synthesized by Balsa and implemented in Synopsys using 180-nm technology.