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1 Novikov S.

1 2007

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Many-Valued Gates for Reducing the Chip-Area of Integrated Circuits

Novikov S.

Studia Informatica : systems and information technology

2007

Vol. 1(8)

7--17

In this paper are proposed new many-valued gates K-PLA, T(2/K) and T(K/2) for a logical synthesis of digital integrated circuits. The semi-custom integrated circuit K-PLA has the architecture of a Programmable Logic Array of a type AND-OR and includes new K-valued valves MAX, MIN and GATE(A,j). A gate T(2/K) ( T(K/2)) is intended for transformation binary (K-valued ) entrance words into K-valued (binary) output words. The method of the logical synthesis with the use K-PLA, T(2/K) and T(K/2) allows to reduce nearly three times the chip-area, which is essential for placing of the circuit’s realization of the system of partial Boolean functions .