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1 2009

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FPGA Implementation of a Numerically Controlled Oscillator with Spur Reduction

Lachowicz S., Pfleiderer H-J.

Electronics and Telecommunications Quarterly

2009

Vol. 55, No 4

617-624

This paper presents a novel method of reducing the spurious signal content in a digitally synthesized sine wave at the output of a numerically controlled oscillator (NCO). The proposed method uses a linear approximation subsystem with a reduced size look-up table (LUT). Two NCO architectures are considered. Architecture 0 - which is the standard -in which the accumulator word length is longer than the LUT address word, is compared with Architecture 1, where the accumulator bits beyond the LUT address space are used for the linear approximation of the value in between the entries of the LUT. Analysis of both architectures demonstrates that the spurious free dynamic range (SFDR) in Architecture 1 equates to 12 dBc per bit of the address space of the LUT as opposed to 6 dBc for Architecture 0. The system was implemented and tested using the Xilinx Spartan 3 platform.