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Effects of Process Related Variations on Defect Formation in Investment Cast Components

Raza M., Silva P., Irwin M., Fagerström B., Jarfors A. E. W.

Archives of Foundry Engineering

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2018

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Vol. 18, iss. 1

103--108

EN

Castability of thin-walled castings is sensitive to variation in casting parameters. The variation in casting parameters can lead to undesired casting conditions which result in defect formation. Variation in rejection rate due to casting defect from one batch to other is common problem in foundries and the cause of this variation usually remain unknown due to complexity of the process. In this work, variation in casting parameters resulting from human involvement in the process is investigated. Casting practices of different groups of casting operators were evaluated and resulting variations in casting parameters were discussed. The effect of these variations was evaluated by comparing the rejection statistics for each group. In order to minimize process variation, optimized casting practices were implemented by developing specific process instructions for the operators. The significance of variation in casting parameters in terms of their impact on foundry rejections was evaluated by comparing the number of rejected components before and after implementation of optimized casting practices. It was concluded that variation in casting parameters due to variation in casting practices of different groups has significant impact on casting quality. Variation in mould temperature, melt temperature and pouring rate due to variation in handling time and practice resulted in varying quality of component from one batch to other. By implementing the optimized casting instruction, both quality and process reliability were improved significantly.

2

Design for reliability: delay faults modeling and simulation for CMOS flip-flops

Cai H., Liu K., An T, Naviner L

International Journal of Microelectronics and Computer Science

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2014

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Vol. 5, nr 3

98--104

EN

Continuously scaling down of CMOS technology brings on low power but also reliability problems such as aggravated aging effects and process variations. They can inﬂuence and degrade the performance of integrated circuits. In recent years, reliability issues of 65nm CMOS node has been intensively studied. In this work, a reliability assessment approach considering aging mechanisms and parametric process variation induced delay fault is proposed in design loop. Negative bias temperature instability (NBTI) and hot carrier injection (HCI) induced degradation are simulated in 65nm ﬂip-ﬂops with different architectures. An example with simple combinational logic (65nm full adder) illustrates this approach for fault probability. It is concluded that process variations are more important comparing to aging effects induced degradation when designing low power digital ﬂip-ﬂops.

3

Model wpływu rozrzutu długości bramek tranzystorów MOS na równomierność rozprowadzania sygnału

Kasprowicz D.

Elektronika : konstrukcje, technologie, zastosowania

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2005

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Vol. 46, nr 10

14-17

PL

Wzrost rozmiarów układów scalonych wymusza stosowanie drzew zegarowych o coraz większej liczbie buforów (wzmacniaczy) regenerujących sygnał zegara. Efektem ubocznym jest jednak silniejszy wpływ rozrzutu opóźnień buforów na rozproszenie sygnału zegara (ang. clock skew). Najistotniejszym składnikiem rozrzutu opóźnień buforów w układach CMOS są zaburzenia długości bramek tranzystorów. W artykule zaproponowano prostą metodę szacowania wpływu tych zaburzeń na rozkład statystyczny rozproszenia sygnału zegara. Przedstawiony model uwzględnia zarówno systematyczne jak i losowe odchylenia długości bramek tranzystorów. Jest przy tym dokładny i wydajny obliczeniowo, co pozwala stosować go w pętli Monte Carlo.

EN

As the dimensions of VLSI circuits grow larger, the number of repeaters (buffers) in clock trees must increase to ensure good clock-signal quality. However, clock skew grows with the number of repeaters as manufacturing variations cause mismatch in repeater delays. The predominant source of repeater delay deviations in CMOS circuits is transistor gate-length variability. This paper describes a simple method for estimating the dependence of clock skew distribution on repeater delay variations as well as on the number of buffering stages and circuit size. The introduced model allows for both systematic and random gate-length variations. The model is accurate and computationally efficient, which makes it a useful tool for Monte Carlo simulations.