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1 International Journal of Microelectronics and Computer Science

1 2013

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A power-balanced sequential element for the delay-based dual-rail precharge logic style

Bongiovanni S, Olivieri M, Scotti G., Trifiletti A.

International Journal of Microelectronics and Computer Science

2013

Vol. 4, nr 4

129--141

Delay-based Dual-rail Pre-charge Logic (DDPL) is a logic style introduced with the aim of hiding power consumption in cryptographic circuits when a Power Analysis (PA) attack is mounted. Its particular data encoding allows to make the adsorbed current constant for each data input combination, irrespective of capacitive load conditions. The purpose is to break the link between dynamic power and data statistics and preventing power analysis. In this work we present a novel implementation of a dynamic differential master-slave ﬂip-ﬂop which is compatible with the DDPL data encoding. Efforts were made in order to design a completely dynamic master-slave architecture which does not require a conversion of the signals from dynamic to static domain. Moreover we show that the area occupied is also reduced due to a compact differential layout. Simulations performed using a 65nm-CMOS process showed that the proposed circuit exhibits good performance in terms of NED (Normalized Energy Deviation) and CV (Coefﬁcient of Variation) of the current samples as required in transistor level countermeasures against power analysis, and it outperforms other previously published DPA-resistant ﬂip-ﬂops in the real case of unbalanced load conditions.