In this paper, we present the idea of using dynamic power estimation during the system-level design. A mixed-signal wireless IC with energy harvesting is used as an example of a device where power exploration and optimization plays a key role during the architecture planning. The novelty of this approach lies in introducing the activity profile for the mixed-signal chip as an important indicator of the power consumption that can drive the design phase. The method presented in this paper is based on modeling of the complete chip in order to apply it with a mixed-language Universal Verification Methodology (UVM) environment. It was decided to use the Verilog-D, SystemVerilog and Verilog-AMS languages to represent behavior of the digital and analog/mixed-signal parts of the chip.
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