Wyniki wyszukiwania - BazTech

Ograniczanie wyników

Znaleziono wyników: 1

Liczba wyników na stronie

Wyniki wyszukiwania

Wyszukiwano:
w słowach kluczowych: power consumption minimisation

Sortuj według:

Ogranicz wyniki do:

Logic Synthesis Method for Power Dissipation Reduction in Combinational Digital Circuits

Brzozowski I., Kos A.

Bulletin of the Polish Academy of Sciences. Technical Sciences

2001

vol. 49, nr 4

581-594

In the paper the authors summerise their works on power dissipation reducing in combinational digital VLSI circuits. The reduction is obtained thanks to proper logic synthesis which consists in the decrease of circuit switching activity and is a part of complex multiobjective optimisation. As a consequence, less complicated, smaller, more reliable and faster digital circuits can be designed. The proposed new synthesis method is illustrated with some examples. The benchmark is included.