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1

Hardware-aware tiling optimization for multi-core systems

Adamski D., Jabłoński G.

Computer Science

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2017

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Vol. 18 (2)

145--162

EN

This paper presents a proposal for a new tool that improves tiling efficiency for a given hardware architecture. This article also describes the correlation between the changing hardware architecture and methods of software optimization. The first chapter includes a short description of the change in hardware architecture that has occurred over the past ten years. The second chapter provides an overview of the tools that will be used in further research. The subsequent sections contain a description of the proposed hardware-aware tool for optimal tiling.

2

Tiling arbitrarily nested loops by means of the transitive closure of dependence graphs

Bielecki W., Pałkowski M.

International Journal of Applied Mathematics and Computer Science

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2016

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Vol. 26, no. 4

919--939

EN

A novel approach to generation of tiled code for arbitrarily nested loops is presented. It is derived via a combination of the polyhedral and iteration space slicing frameworks. Instead of program transformations represented by a set of affine functions, one for each statement, it uses the transitive closure of a loop nest dependence graph to carry out corrections of original rectangular tiles so that all dependences of the original loop nest are preserved under the lexicographic order of target tiles. Parallel tiled code can be generated on the basis of valid serial tiled code by means of applying affine transformations or transitive closure using on input an inter-tile dependence graph whose vertices are represented by target tiles while edges connect dependent target tiles. We demonstrate how a relation describing such a graph can be formed. The main merit of the presented approach in comparison with the well-known ones is that it does not require full permutability of loops to generate both serial and parallel tiled codes; this increases the scope of loop nests to be tiled.

3

Polyhedral Source-to-Source Compile

Adamski D., Jabłoński G., Perek P., Napieralski A.

Elektronika : konstrukcje, technologie, zastosowania

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2016

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Vol. 57, nr 12

3--13

EN

This paper describes a novel Polyhedral Source-to-Source Compiler (PSSC) that enables automatic recognition of parallel regions of C/C++ code and annotating them with OpenMP/OpenACC pragmas. The proposed source-to-source compiler uses polyhedral model to detect and optimize parallel loops. Loop optimization is done on intermediate code representation by Polly compiler and then it is mapped to original source code. This approach allows combining the simplicity and efficiency of Intermediate Representation (IR) code optimization with readability of output code. Experimental results show that the proposed compiler is able to reach the comparable performance to the original Polly compiler.

PL

Artykuł opisuje nowatorski kompilator typu source-to-source, który wykorzystuje model polihedralny do automatycznego wykrywania kodu C/C++, który może być wykonywany równolegle. Fragmenty kodu źródłowego, które mogą zostać zrównoleglone, są opatrywane pragmami OpenMP/OpenACC. Opisywany kompilator śledzi zmiany jakie zostały wprowadzone w kodzie pośrednim przez kompilator Polly, a następnie odwzoruje te transformacje w kodzie źródłowym. Przedstawione w artykule podejście umożliwia połączenie zalet wynikających z optymalizowania kodu pośredniego z możliwością łatwego przenoszenia na różne platformy kodu wysokopoziomowego. Przeprowadzone pomiary wydajności wykazały, że opracowany kompilator pozwala zrównoleglić kod wysokopoziomowy równie wydajnie jak bazowy kompilator Polly.