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1 International Journal of Microelectronics and Computer Science

1 2015

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Spice simulation of substrate potential shift in HVCMOS technologies

Stefanucci C., Buccella P., Kayal M., Sallese J.-M.

International Journal of Microelectronics and Computer Science

2015

Vol. 6, nr 4

142--147

High voltage CMOS active devices inherently include a parasitic vertical PNP bipolar transistor. When activated it injects holes into the substrate causing a dangerous potential shift. In this work a spice-modeling approach based on transistor layout is presented to simulate substrate de-biasing in Smart Power ICs. The proposed model relies on a parasitic substrate network without the need of a parasitic BJT in HVCMOS compact models. The results are compared with TCAD simulations at different temperatures showing good agreement. Potential shift of the substrate is analysed for different geometrical configurations to estimate the effect of P+ grounding schemes and backside contact.