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Fir Filters Compliant with the IEEE Standard for M Class PMU

Duda K., Zieliński T. P.

Metrology and Measurement Systems

2016

Vol. 23, nr 4

623--636

In this paper it is shown that M class PMU (Phasor Measurement Unit) reference model for phasor estimation recommended by the IEEE Standard C37.118.1 with the Amendment 1 is not compliant with the Standard. The reference filter preserves only the limits for TVE (total vector error), and exceeds FE (frequency error) and RFE (rate of frequency error) limits. As a remedy we propose new filters for phasor estimation for M class PMU that are fully compliant with the Standard requirements. The proposed filters are designed: 1) by the window method; 2) as flat-top windows; or as 3) optimal min-max filters. The results for all Standard compliance tests are presented, confirming good performance of the proposed filters. The proposed filters are fixed at the nominal frequency, i.e. frequency tracking and adaptive filter tuning are not required, therefore they are well suited for application in lowcost popular PMUs.

Wykorzystanie modułu FPGA platformy sprzętowej sbRIO-9602 do obliczania fazora z zastosowaniem DFT

Barczentewicz S., Nabielec J.

Pomiary Automatyka Kontrola

2014

R. 60, nr 3

141--143

Praca dotyczy problemu implementacji algorytmu obliczania fazora w jednym układzie scalonym FPGA-SPARTAN, w którym jednocześnie zaimplementowany jest protokół komunikacyjny czasu rzeczywistego dostosowany do PSS (Power Stabilization System). Przedstawione rozwiązanie pozwala na implementację takich obliczeń z możliwie najmniejszą objętością zajmowanych zasobów FPGA i przy jak najmniejszych błędach obliczeniowych. Algorytm obliczeń oparty został o dyskretne przekształcenie Fouriera.

This work presents a novel approach to implementation of the phasor estimation algorithm using a single FPGA module, with simultaneous communication protocol compatible with Power Stabilization System on it. The presented implementation allows for calculations using as little resources as possible. This paper is organized as follows. In Section 1 the definitions and convention of graphical representation of phasor and synchrophasor (Fig. 1) given by [1] are quoted. Moreover, the definition of discrete Fourier transform is recalled [4], for explanation of its usage in the presented algorithm. In Section 2 the programming environment LabVIEW FPGA and the used instrumentation (sbRIO-9602 platform with FPGA module Xilinx Spartan, ADC converter NI9215E) are described. Furthermore, the proposed algorithm of phasor estimation is presented. Figure 2 shows the simplified block diagram of the designed algorithm. Afterwards, the methodology and results from the conducted tests are listed. Table 1 presents the resources utilization statistics of FPGA, and Table 2 shows the compilation of the test results of computational errors of module and phase estimation. Phasor estimation algorithm is based on DFT computation, and more specifically only one DFT bin is used when sampling frequency and observation length are known. Algorithm uses this fact to minimize demand for FPGA resources. Conducted tests showed that the main problem with obtaining high accuracy of algorithm is limited precision of fixed-point calculations.