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Basic Aspects of Designing a High-performance Processor Structure for Calculating a "true" Discrete Fractional Fourier Transform

Cariow A., Majorkowska-Mech D.

Measurement Automation Monitoring

2018

Vol. 64, No. 2

43--45

This paper presents a basic aspects of structural design of the highperformance processor for implementation of discrete fractional Fourier transform (DFrFT). The general idea of the possibility of parallelizing the calculation of the so-called “true” discrete Fourier transform on the basis of our previously developed algorithmic approach is presented. We specifically focused only on the general aspects of the organization of the structure of such a processor, since the details of a particular implementation always depend on the implementation platform used, while the general idea of constructing the structure of the processor remains unchanged.

Parallelization of computations for generating combinations

Novikov S.

Studia Informatica : systems and information technology

2017

Vol. 1-2(21)

47--62

An effective sequential algorithm and two parallel algorithms for generating combinations without repetitions of m out n of objects, represented by Boolean vectors, are proposed. One of them allows one to calculate starting and ending combinations for the subset, generated by each computing processor. The second algorithm firstly generates short (m-component) vectors on several computing processors. After that, by using special [n/m]-component vectors, it connects the short vectors into n-component Boolean vectors, each of which containing of exactly m units.