Offered algorithm allows to build the structure of the parallel pipeline FFT processors (PPFFT-processor) computing the vector DFT in real time with the minimum structural complexity at given parameters : speed of input data receipt ; structure of a computing element (arhimetic device) and time of the butterfly operation execution. The considered approach to structural synthesis of the PPFFT-processors for R-dimensional signal processing allows to receive the structure of the processor under given restrictions of a specific problem and is the basis for solving the questions of automated design of PPFFT-processors at a structural level.
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