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Content available remote Scaling of nonvolatile memories to nanoscale feature sizes
EN
he market for nonvolatile memory devices is growing rapidly. Today, the vast majority of nonvolatile memory devices are based on the floating gate device which is facing serious scaling limitations. Material innovations currently under investigation to extend the scalability of floating gate devices are discussed. An alternative path is to replace the floating gate by a charge trapping material. The combination of charge trapping and localized channel hot electron injection allows storing two physically separated bits in one memory cell. The current status and prospects of charge trapping devices are reviewed, demonstrating their superior scalability. Floating gate as well as charge trapping memory cells suffer from severe performance limitations with respect to write and erase speed and endurance driving system overhead. A memory that works like random access memory and is nonvolatile would simplify system design. This, however, calls for new switching effects that are based on integrating new materials into the memory cell. An outlook to memory concepts that use ferroelectric switching, magnetic switching, phase change, or other resistive switching effects is given, illustrating how the integration of new materials may solve the limitations of today's semiconductor memory concepts.
2
Content available remote Nanocluster memories by ion beam synthesis of Si in SiO2
EN
Ion implantation and ion irradiation induced interface mixing were used to synthesise silicon nanoclusters in the gate oxide of metal-oxide-semiconductor (MOS) structures aiming at electronic memory applications. In the present study silicon nanocrystals for multi-dot floating-gate memories produced by ion irradiation through SiO2/Si nterfaces have been investigated to demonstrate possible advantages of this approach compared to conventional application of ion beam synthesis to the fabrication of silicon nanocrystal memories. The memory properties of the fabricated structures as a function of Si+-irradiation dose and post-irradiation annealing temperature and time have been examined through electrical measurements on n-channel MOS field-effect transistors. Low-voltage operating devices that can endure more than 106 programming/erasing cycles have been successfully achieved. More research is still required to improve charge retention and ensure the standard 10-year retention time needed for true non-volatile memory applications.
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