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Thermal modelling of modern processors using FEM and compact model

Galicia M., Zając P., Maj C., Szermer M., Napieralski A.

International Journal of Microelectronics and Computer Science

2015

Vol. 6, nr 3

110--116

A variety of thermal models has been proposed to predict the temperatures inside modern processors. In this paper, we describe and compare two such approaches, a detailed FEMbased simulation and a simpler architectural compact model. It is shown that both models provide comparable results when it comes to predicting the maximal temperature, however there are also non-negligible differences when estimating thermal gradients within a chip. Furthermore, transient simulation results show some differences in temperature profile during processor heating.

Multi Queue Approach for Network Services Implemented for Multi Core CPUs

Hasse M., Nowicki K., Woźniak J.

Journal of Telecommunications and Information Technology

2011

nr 3

57-62

Multiple core processors have already became the dominant design for general purpose CPUs. Incarnations of this technology are present in solutions dedicated to such areas like computer graphics, signal processing and also computer networking. Since the key functionality of network core components is fast package servicing, multicore technology, due to multi tasking ability, seems useful to support packet processing. Dedicated network processors characterize very good performance but at the same time high cost. General purpose CPUs achieve incredible performance, thanks to task distribution along several available cores and relatively low cost. The idea, analyzed in this paper, is to use general purpose CPU to provide network core functionality. For this purpose parameterized system model has been created, which represents general core networking needs. This model analyze system parameters influence on system performance.

Optimization of a modular neural network for pattern recognition using parallel genetic algorithm

Cárdenas M., Melin P., Cruz L.

Journal of Automation Mobile Robotics and Intelligent Systems

2011

Vol. 5, No. 1

77-84

In this paper, the implementation of a Parallel Genetic Algorithm (PGA) for the training stage, and the optimi zation of a monolithic and modular neural network, for pattern recognition are presented. The optimization con sists in obtaining the best architecture in layers, and neu rons per layer achieving the less training error in a shor ter time. The implementation was performed in a multicore architecture, using parallel programming techniques to exploit its resources. We present the results obtained in terms of performance by comparing results of the training stage for sequential and parallel implementations.