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CLP approach to optimal instruction scheduling for VLIW processors

Domagała Ł.

Archives of Control Sciences

2009

Vol. 19, no. 2

127-149

Along with modern processor architectures where multiple functional units can execute instructions in parallel and numerous resources have to be managed, there is a need for efficient tools facilitating code generation and enhancing development. The aim is to achieve maximal instruction throughput. This is a place where automatic optimization techniques should be employed due to high complexity of the real life problems. This article presents an approach to optimal instruction scheduling for very long instruction word (VLIW) processors using a constraint logic programming (CLP) solver with particular emphasis on the modulo scheduling technique. Modulo scheduling is an optimization technique used to achieve greater instruction level parallelism than one achievable by just optimally scheduling code basic blocks.