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A new architecture of thermometer to binary code encoder for 4 - bit FLASH ADC in 45nm CMOS process

Sam D.S.Shylu, Paul P. Sam, Reddy Golamari Kiran Kumar, Manideep Nagothu, Venkatesh Nethikuntla Chakali, Manideep Pulikonda Durga Sai

Przegląd Elektrotechniczny

2023

R. 99, nr 11

188--191

In this work, a new architecture of Thermometer to Binary Encoder is designed in 45nm CMOS Technology for 4-bit FLASH ADC. The Thermometer code is converted to intermediate gray code and then to binary code in the proposed encoder. The 4-bit FLASH ADC is integrated with the proposed low –power encoder, Double-tail Dynamic Comparator and resistive ladder networks. Simulation results show that the proposed encoder consumes 119μW power with 1V supply voltage. The 4-bit FLASH ADC consumes less power when compared with the conventional ADCs.

W tej pracy zaprojektowano nową architekturę termometru do kodera binarnego w technologii 45nm CMOS dla 4-bitowego FLASH ADC. Kod termometru jest konwertowany na pośredni kod Graya, a następnie na kod binarny w proponowanym enkoderze. 4-bitowy FLASH ADC jest zintegrowany z proponowanym koderem małej mocy, dwustronnym komparatorem dynamicznym i rezystancyjnymi sieciami drabinkowymi. Wyniki symulacji pokazują, że proponowany enkoder pobiera moc 119μW przy napięciu zasilania 1V. 4-bitowy FLASH ADC zużywa mniej energii w porównaniu z konwencjonalnymi przetwornikami ADC.

A 2.3-dB NF CMOS low voltage LNA optimized for medical applications at 600MHz

Borrego R

International Journal of Microelectronics and Computer Science

2013

Vol. 4, nr 3

87--91

In this paper it is presented a balun LNA, with voltage gain control that combines a common-gate and common-source stage, in which transistors biased in triode region replace the resistive loads. This last approach in conjunction with a dynamic threshold reduction technique allows a low supply voltage operation. Furthermore, a signiﬁcant chip area reduction can be exploited by adopting an inductor-less configuration. Simulations results with a 130 nm CMOS technology show that the gain is up to 19.3 dB and the NF is below 2.3 dB. The total dissipation is 4 mW, leading to an FOM of 2.26 for 0.6 V supply.

Low-power open loop multiply-by-two amplifier with gain-accuracy improved by local-feedback

Gama R., Galhardo A., Goes J., Paulino R., Neves R., Horta N.

International Journal of Microelectronics and Computer Science

2010

Vol. 1, nr 1

19-24

This paper proposes the complete electrical design of a new multiply-by-two amplifier to be readily used in ultra high-speed medium resolution pipeline ADC stages. It is based in a switched-capacitor open-loop structure but with the novelty of having the gain accuracy improved by using an active amplifier with local feedback. Simulation results demonstrate that, with a very low-power dissipation and without employing any digital self-calibration or gain-control techniques, the circuit exhibits, over PVT corner and device mismatches, a dynamic performance and a gain-accuracy compatible with 6-bit level.