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Transformacja rozmytej interpretowanej sieci Petriego na schemat układu logicznego

Gniewek L.

Pomiary Automatyka Kontrola

2010

R. 56, nr 11

1368-1371

W pracy przedstawiono teoretyczne podstawy nowego rodzaju rozmytej, interpretowanej sieci Petriego, opisując i uzasadniając zaproponowaną strukturę topologiczną i jej interpretację. Przedstawiono użyteczną w praktyce metodę odwzorowania układowego tej sieci, podając konkretny sposób transformacji jej diagramu na schemat logiczny, zbudowany z rozmytych elementów kombinacyjnych i sekwencyjnych. Schemat ten może być podstawą do generowania kodu programu sterującego dla sterowników przemysłowych PLC.

The fuzzy Petri nets are applied above all as advisory or monitoring systems. The nets take into account both binary and multivalued (analog) signals appearing in the observed system. Only a few works are devoted to using these nets directly for control [3, 4, 5]. The fuzzy interpreted Petriego net defined in this paper belongs to low-level nets, used for modelling systems based on FPGA devices or industrial controllers. The net enables presenting the control algorithm in a graphical (diagram of the net) or algebraic (incidence matrix) form [7], which makes the analysis of its properties already at the stage of the abstract synthesis easier. Moreover, this net allows including quantitative changes occurring in the system, not losing natural interpretation of transferring the marker through the transition. In the paper basic definitions of the fuzzy interpreted Petriego net describing the net construction and functioning are given. The transformation method of this net into a logic circuit based on fuzzy combinational and sequential circuits is proposed. All essential elements for this conversion, i.e. the modified fuzzy SR flip-flop (8), the activation circuit (Fig. 2) and the fuzzy gate based on bounded product (6) are described. The examples of connecting these elements are shown (Figs. 3 - 6) and a manner of their synchronization is described. The logic circuit obtained in this way can be a basis for generating the code of the control program for industrial controllers and lead to partial automation of this process.

Many-Valued Gates for Reducing the Chip-Area of Integrated Circuits

Novikov S.

Studia Informatica : systems and information technology

2007

Vol. 1(8)

7--17

In this paper are proposed new many-valued gates K-PLA, T(2/K) and T(K/2) for a logical synthesis of digital integrated circuits. The semi-custom integrated circuit K-PLA has the architecture of a Programmable Logic Array of a type AND-OR and includes new K-valued valves MAX, MIN and GATE(A,j). A gate T(2/K) ( T(K/2)) is intended for transformation binary (K-valued ) entrance words into K-valued (binary) output words. The method of the logical synthesis with the use K-PLA, T(2/K) and T(K/2) allows to reduce nearly three times the chip-area, which is essential for placing of the circuit’s realization of the system of partial Boolean functions .